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symfpu: Verifying rounding modes
Works for everything but muladd. Which I saw coming, but am still frustrated by.
This commit is contained in:
Krystine Sherwin
parent
9db187469d
commit
5c99ff204b
3 changed files with 75 additions and 59 deletions
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@ -1 +1 @@
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Subproject commit ac38165068f507d2b46ad16b870272f0ca5a6c0a
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Subproject commit 7ef44ec4a91de1635b3c837dc00ea5b570b3e871
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@ -64,6 +64,7 @@ module edges();
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wire o_norm = o_exp > 8'h00 && !o_special;
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wire o_subnorm = o_exp == 8'h00 && o_sig != '0;
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wire o_finite = o_norm || o_subnorm;
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wire o_unclamped = o_finite && o_unsigned != 31'h7f7fffff;
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`ifdef MULADD
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wire muladd_zero = c_zero;
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@ -133,20 +134,50 @@ module edges();
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wire lhs_dominates = lhs_exp > rhs_exp;
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wire [7:0] exp_diff = lhs_dominates ? lhs_exp - rhs_exp : rhs_exp - lhs_exp;
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wire round_p_001 = 0;
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wire round_p_011 = a == 32'h40400000 && b == 32'h40000001;
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wire round_n_011 = 0;
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wire round_n_011 = a == 32'hc0400000 && b == 32'h40000001;
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wire round_p_001, round_p_011, round_n_001, round_n_011;
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wire [30:0] rounded_100, rounded_010, rounded_000;
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wire [30:0] rounded_100 = 31'h40C00002;
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wire [30:0] rounded_010 = 31'h40C00001;
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wire [30:0] rounded_000 = 31'h40C00000;
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`ifdef MUL
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assign round_p_001 = 0;
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assign round_p_011 = a == 32'h40400000 && b == 32'h40000001;
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assign round_n_001 = 0;
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assign round_n_011 = a == 32'hc0400000 && b == 32'h40000001;
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assign rounded_100 = 31'h40C00002;
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assign rounded_010 = 31'h40C00001;
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assign rounded_000 = 31'h40C00000;
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`elsif ADD
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assign round_p_001 = a == 32'h4c000000 && b == 32'h40000000;
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assign round_p_011 = a == 32'h4c000001 && b == 32'h40000000;
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assign round_n_001 = a == 32'hcc000000 && b == 32'hc0000000;
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assign round_n_011 = a == 32'hcc000001 && b == 32'hc0000000;
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assign rounded_100 = 31'h4C000002;
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assign rounded_010 = 31'h4C000001;
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assign rounded_000 = 31'h4C000000;
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`else
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assign round_p_001 = 0;
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assign round_p_011 = 0;
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assign round_n_001 = 0;
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assign round_n_011 = 0;
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assign rounded_100 = '0;
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assign rounded_010 = '0;
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assign rounded_000 = '0;
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`endif
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always @* begin
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if (a_nan)
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if (a_nan || b_nan || c_nan) begin
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// input NaN = output NaN
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assert (o_nan);
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// NaN inputs give NaN outputs, do not raise exceptions (unless signaling NV)
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// assert (!DZ);
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// assert (!OF);
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// assert (!UF);
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// assert (!NX);
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end
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if (a_snan)
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// signalling NaN raises invalid exception
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assert (NV);
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@ -179,7 +210,6 @@ module edges();
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assert (o_inf);
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`elsif RTP
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if (OF) // output = +inf or -max
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// RTP add is raising inexact overflow for NaN input
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assert (o == pos_inf || o == neg_max);
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if (o == neg_inf)
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assert (!OF);
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@ -208,6 +238,7 @@ module edges();
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assert (!NX);
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`ifdef DIV
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assume (c_zero);
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// a = finite, b = 0
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if ((a_norm || a_subnorm) && b_unsigned == '0)
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assert (DZ);
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@ -231,6 +262,10 @@ module edges();
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end
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`endif
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`ifdef MUL
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assume (c_zero);
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`endif
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`ifdef MULS
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// 0/inf or inf/0
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if ((a_inf && b_zero) || (a_zero && b_inf))
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@ -242,16 +277,18 @@ module edges();
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if (a_norm && a_exp < 8'h60 && b_subnorm && !c_special) begin
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assert (NX);
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`ifdef MULADD
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assert (UF || (c_zero ? o_zero : o == c));
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// within rounding
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assert (UF || (c_zero ? o_zero : (o == c || o == c+1 || o == c-1)));
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`else
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assert (UF || o_zero);
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`endif
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if (o_zero)
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assert (o_sign == a_sign ^ b_sign);
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`endif
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end
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`endif
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`ifdef ADDSUB
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assume (c_zero);
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// adder can't underflow, subnormals are always exact
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assert (!UF);
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`endif
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@ -259,27 +296,27 @@ module edges();
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`ifdef RNE
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if (round_p_001) assert (o_unsigned == rounded_000);
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if (round_p_011) assert (o_unsigned == rounded_100);
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if (round_n_011) assert (o_unsigned == rounded_000);
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if (round_n_001) assert (o_unsigned == rounded_000);
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if (round_n_011) assert (o_unsigned == rounded_100);
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`elsif RNA
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if (round_p_001) assert (o_unsigned == rounded_010);
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if (round_p_011) assert (o_unsigned == rounded_100);
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if (round_n_011) assert (o_unsigned == rounded_010);
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if (round_n_001) assert (o_unsigned == rounded_010);
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if (round_n_011) assert (o_unsigned == rounded_100);
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`elsif RTP
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if (round_p_001) assert (o_unsigned == rounded_010);
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if (round_p_011) assert (o_unsigned == rounded_100);
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if (round_n_011) assert (o_unsigned == rounded_000);
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if (round_n_001) assert (o_unsigned == rounded_000);
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if (round_n_011) assert (o_unsigned == rounded_010);
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`elsif RTN
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if (round_p_001) assert (o_unsigned == rounded_000);
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if (round_p_011) assert (o_unsigned == rounded_010);
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if (round_n_011) assert (o_unsigned == rounded_010);
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if (round_n_001) assert (o_unsigned == rounded_010);
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if (round_n_011) assert (o_unsigned == rounded_100);
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`elsif RTZ
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if (round_p_001) assert (o_unsigned == rounded_000);
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if (round_p_011) assert (o_unsigned == rounded_010);
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if (round_n_011) assert (o_unsigned == rounded_000);
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if (round_n_001) assert (o_unsigned == rounded_000);
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if (round_n_011) assert (o_unsigned == rounded_010);
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`endif
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@ -298,7 +335,7 @@ module edges();
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if (!UF) begin
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// for a small difference in exponent with zero LSB, the result must be
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// exact
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if (o_finite && lhs_dominates && exp_diff < 8'd08 && rhs_sig[7:0] == 0 && lhs_sig[7:0] == 0)
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if (o_unclamped && lhs_dominates && exp_diff < 8'd08 && rhs_sig[7:0] == 0 && lhs_sig[7:0] == 0)
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assert (!NX);
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if (exp_diff == 0 && !OF && lhs_sig[7:0] == 0 && rhs_sig[7:0] == 0)
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assert (!NX);
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@ -338,6 +375,8 @@ module edges();
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`endif
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`ifdef SQRT
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assume (b_zero);
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assume (c_zero);
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// complex roots are invalid
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if (a_sign && (a_norm || a_subnorm))
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assert (NV);
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@ -3,63 +3,40 @@ set -eu
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source ../gen-tests-makefile.sh
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# operators
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ops="sqrt add sub mul div muladd"
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for op in $ops; do
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rm -f ${op}_edges.*
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done
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rm -f *_edges.*
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prove_op() {
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prove_rm() {
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op=$1
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defs=$2
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ys_file=${op}_edges.ys
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rm=$2
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defs=$3
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ys_file=${op}_${rm}_edges.ys
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echo """\
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symfpu -op $op
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symfpu -op $op -rm $rm
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sat -prove-asserts -verify
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chformal -remove
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opt
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read_verilog -sv -formal $defs edges.sv
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read_verilog -sv -formal $defs -D${rm} edges.sv
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chformal -lower
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prep -top edges -flatten
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sat -prove-asserts -verify
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sat -set-assumes -prove-asserts -verify
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""" > $ys_file
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}
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prove_op() {
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op=$1
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defs=$2
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rms="RNE RNA RTP RTN RTZ"
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for rm in $rms; do
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prove_rm $op $rm "$defs"
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done
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}
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prove_op sqrt "-DSQRT"
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prove_op add "-DADD -DADDSUB -DADDS"
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prove_op sub "-DSUB -DADDSUB -DADDS"
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prove_op mul "-DMUL -DMULS"
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prove_op div "-DDIV"
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prove_op muladd "-DMULADD -DMULS -DADDS"
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# rounding modes
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rms="RNE RNA RTP RTN RTZ"
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for rm in $rms; do
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rm -f ${rm}_edges.*
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done
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prove_rm() {
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rm=$1
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defs=$2
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ys_file=${rm}_edges.ys
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echo """\
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symfpu -rm $rm
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sat -prove-asserts -verify
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chformal -remove
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opt
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read_verilog -sv -formal $defs edges.sv
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chformal -lower
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prep -top edges -flatten
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sat -prove-asserts -verify
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""" > $ys_file
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}
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prove_rm RNE "-DRNE"
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prove_rm RNA "-DRNA"
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prove_rm RTP "-DRTP"
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prove_rm RTN "-DRTN"
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prove_rm RTZ "-DRTZ"
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# prove_op muladd "-DMULADD -DMULS -DADDS"
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generate_mk --yosys-scripts
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