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Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf

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This commit is contained in:
Eddie Hung 2019-10-05 09:27:12 -07:00
parent b47bb5c810
commit 5c68da4150
2 changed files with 26 additions and 0 deletions
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4
passes/pmgen/ice40_wrapcarry.pmg
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@ -9,3 +9,7 @@ match lut
index <SigSpec> port(lut, \I1) === port(carry, \I0) index <SigSpec> port(lut, \I1) === port(carry, \I0)
index <SigSpec> port(lut, \I2) === port(carry, \I1) index <SigSpec> port(lut, \I2) === port(carry, \I1)
endmatch endmatch
code
accept;
endcode

22
tests/ice40/wrapcarry.ys Normal file
View file

@ -0,0 +1,22 @@
read_verilog <<EOT
module top(input A, B, CI, output O, CO);
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
SB_LUT4 #(
.LUT_INIT(16'b 0110_1001_1001_0110)
) adder (
.I0(1'b0),
.I1(A),
.I2(B),
.I3(1'b0),
.O(O)
);
endmodule
EOT
ice40_wrapcarry
select -assert-count 1 t:$__ICE40_CARRY_WRAPPER