mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 16:45:32 +00:00
Code Activity

Docs: $eqx aka case equality

Browse source
This commit is contained in:
Krystine Sherwin 2024-09-05 16:10:28 +12:00
parent 217c2a15dd
commit 5c4f7b4deb
No known key found for this signature in database
2 changed files with 5 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

2
docs/source/cell/word_binary.rst
View file

@ -14,8 +14,6 @@ Binary operators
shiftx, div, mod, pmux (less-so) can produce 'x' output even if all inputs
are defined
.. todo:: `$eqx` is the case equality operator
All binary RTL cells have two input ports ``A`` and ``B`` and one output port
``Y``. They also have the following parameters: