mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 19:52:31 +00:00 
			
		
		
		
	Fix normal (non-array) hierarchy -auto-top.
Add simple test.
This commit is contained in:
		
							parent
							
								
									5c504c5ae6
								
							
						
					
					
						commit
						5c4a72c43e
					
				
					 3 changed files with 74 additions and 10 deletions
				
			
		
							
								
								
									
										56
									
								
								tests/various/hierarchy.sh
									
										
									
									
									
										Normal file
									
								
							
							
						
						
									
										56
									
								
								tests/various/hierarchy.sh
									
										
									
									
									
										Normal file
									
								
							|  | @ -0,0 +1,56 @@ | |||
| #!/usr/bin/env bash | ||||
| # Simple test of hierarchy -auto-top. | ||||
| 
 | ||||
| set -e | ||||
| 
 | ||||
| ../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module" | ||||
|   read_verilog << EOV | ||||
|     module TOP(a, y); | ||||
|       input a; | ||||
|       output [31:0] y; | ||||
| 
 | ||||
|       aoi12 p [31:0] (a, y); | ||||
|     endmodule | ||||
| 
 | ||||
|     module aoi12(a, y); | ||||
|       input a; | ||||
|       output y; | ||||
|       assign y = ~a; | ||||
|     endmodule | ||||
|   EOV | ||||
|   hierarchy -auto-top | ||||
| EOY | ||||
| 
 | ||||
| ../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module" | ||||
|   read_verilog << EOV | ||||
|     module aoi12(a, y); | ||||
|       input a; | ||||
|       output y; | ||||
|       assign y = ~a; | ||||
|     endmodule | ||||
| 
 | ||||
|     module TOP(a, y); | ||||
|       input a; | ||||
|       output [31:0] y; | ||||
| 
 | ||||
|       aoi12 foo (a, y); | ||||
|     endmodule | ||||
|   EOV | ||||
|   hierarchy -auto-top | ||||
| EOY | ||||
| 
 | ||||
| ../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected noTop as design top module." | ||||
|   read_verilog << EOV | ||||
|     module aoi12(a, y); | ||||
|       input a; | ||||
|       output y; | ||||
|       assign y = ~a; | ||||
|     endmodule | ||||
| 
 | ||||
|     module noTop(a, y); | ||||
|       input a; | ||||
|       output [31:0] y; | ||||
|     endmodule | ||||
|   EOV | ||||
|   hierarchy -auto-top | ||||
| EOY | ||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue