diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 8f1b07b10..cdd0ed802 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1464,7 +1464,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		log("Importing module %s.\n", RTLIL::id2cstr(module->name));
 	}
 	import_attributes(module->attributes, nl, nl);
-	module->set_string_attribute(ID::hdlname, nl->CellBaseName());
+	if (module->name.isPublic())
+		module->set_string_attribute(ID::hdlname, nl->CellBaseName());
 	module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
 #ifdef VERIFIC_VHDL_SUPPORT
 	if (nl->IsFromVhdl()) {
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index cb0f7da78..f0418c5d7 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2183,6 +2183,20 @@ void RTLIL::Module::sort()
 		it.second->attributes.sort(sort_by_id_str());
 }
 
+void check_hdl_scope_names(IdString name, RTLIL::AttrObject* obj) {
+	if(name.isPublic() || name.begins_with("$paramod") || name.begins_with("$abstract")) {
+		if(obj->has_attribute(ID(scopename))) {
+			log("Object with public name '%s' should not have scopename attribute.\n", name.c_str());
+			log_assert(!((name.isPublic() || name.begins_with("$paramod") || name.begins_with("$abstract")) && obj->has_attribute(ID(scopename))));
+		}
+	} else {
+		if(obj->has_attribute(ID::hdlname)) {
+			log("Object with private name '%s' should not have hdlname attribute.\n", name.c_str());
+			log_assert(!(!(name.isPublic() || name.begins_with("$paramod") || name.begins_with("$abstract")) && obj->has_attribute(ID::hdlname)));
+		}
+	}
+}
+
 void RTLIL::Module::check()
 {
 #ifndef NDEBUG
@@ -2205,6 +2219,7 @@ void RTLIL::Module::check()
 			ports_declared[it.second->port_id-1] = true;
 		} else
 			log_assert(!it.second->port_input && !it.second->port_output);
+		check_hdl_scope_names(it.first, it.second);
 	}
 	for (auto port_declared : ports_declared)
 		log_assert(port_declared == true);
@@ -2217,6 +2232,7 @@ void RTLIL::Module::check()
 		log_assert(it.second->size >= 0);
 		for (auto &it2 : it.second->attributes)
 			log_assert(!it2.first.empty());
+		check_hdl_scope_names(it.first, it.second);
 	}
 
 	pool<IdString> packed_memids;
@@ -2244,6 +2260,7 @@ void RTLIL::Module::check()
 			log_assert(!packed_memids.count(memid));
 			packed_memids.insert(memid);
 		}
+		check_hdl_scope_names(it.first, it.second);
 	}
 
 	for (auto &it : processes) {
@@ -2288,6 +2305,8 @@ void RTLIL::Module::check()
 
 	for (auto &it : attributes)
 		log_assert(!it.first.empty());
+
+	check_hdl_scope_names(name, this);
 #endif
 }
 
diff --git a/kernel/scopeinfo.h b/kernel/scopeinfo.h
index f3ae0d7b6..85cf0c85c 100644
--- a/kernel/scopeinfo.h
+++ b/kernel/scopeinfo.h
@@ -337,7 +337,7 @@ template<typename O>
 std::vector<IdString> parse_hdlname(const O* object)
 {
 	std::vector<IdString> path;
-	if (!object->name.isPublic())
+	if (!object->name.isPublic() && !object->name.begins_with("$paramod") && !object->name.begins_with("$abstract"))
 		return path;
 	for (auto const &item : object->get_hdlname_attribute())
 		path.push_back("\\" + item);
@@ -351,7 +351,7 @@ std::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)
 {
 	std::vector<IdString> path;
 	IdString trailing = object->name;
-	if (object->name.isPublic()) {
+	if (object->name.isPublic() || object->name.begins_with("$paramod") || object->name.begins_with("$abstract")) {
 		for (auto const &item : object->get_hdlname_attribute())
 			path.push_back("\\" + item);
 		if (!path.empty()) {
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 6114dd34b..e72765559 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -377,6 +377,10 @@ static void extract_fsm(RTLIL::Wire *wire)
 	fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
 	fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
 	fsm_cell->attributes = wire->attributes;
+	if(fsm_cell->attributes.count(ID::hdlname)) {
+		fsm_cell->attributes[ID(scopename)] = fsm_cell->attributes[ID::hdlname];
+		fsm_cell->attributes.erase(ID::hdlname);
+	}
 	fsm_data.copy_to_cell(fsm_cell);
 
 	// rename original state wire
@@ -384,6 +388,10 @@ static void extract_fsm(RTLIL::Wire *wire)
 	module->wires_.erase(wire->name);
 	wire->attributes.erase(ID::fsm_encoding);
 	wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
+	if(wire->attributes.count(ID::hdlname)) {
+		wire->attributes[ID(scopename)] = wire->attributes[ID::hdlname];
+		wire->attributes.erase(ID::hdlname);
+	}
 	module->wires_[wire->name] = wire;
 
 	// unconnect control outputs from old drivers