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Fix and test for balanced case

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This commit is contained in:
Eddie Hung 2019-06-06 14:21:34 -07:00
parent 0a66720f6f
commit 5c277c6325
3 changed files with 55 additions and 10 deletions
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22
passes/opt/muxpack.cc
View file

@ -94,23 +94,27 @@ struct MuxpackWorker
{ {
log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type)); log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
SigSpec next_sig = cell->getPort("\\A"); SigSpec a_sig = cell->getPort("\\A");
if (sig_chain_prev.count(next_sig) == 0) {
if (cell->type == "$mux") { if (cell->type == "$mux") {
next_sig = cell->getPort("\\B"); SigSpec b_sig = cell->getPort("\\B");
if (sig_chain_prev.count(next_sig) == 0) if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
goto start_cell; goto start_cell;
}
else if (!sig_chain_prev.count(a_sig))
a_sig = b_sig;
}
else if (cell->type == "$pmux") {
if (!sig_chain_prev.count(a_sig))
goto start_cell; goto start_cell;
} }
else log_abort();
{ {
for (auto bit : next_sig.bits()) for (auto bit : a_sig.bits())
if (sigbit_with_non_chain_users.count(bit)) if (sigbit_with_non_chain_users.count(bit))
goto start_cell; goto start_cell;
Cell *c1 = sig_chain_prev.at(next_sig); Cell *c1 = sig_chain_prev.at(a_sig);
Cell *c2 = cell; Cell *c2 = cell;
if (c1->getParam("\\WIDTH") != c2->getParam("\\WIDTH")) if (c1->getParam("\\WIDTH") != c2->getParam("\\WIDTH"))

26
tests/various/muxpack.v
View file

@ -110,3 +110,29 @@ always @* begin
endcase endcase
end end
endmodule endmodule
module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s[0] == 1'b0)
if (s[1] == 1'b0)
if (s[2] == 1'b0)
o <= i[0*W+:W];
else
o <= i[1*W+:W];
else
if (s[2] == 1'b0)
o <= i[2*W+:W];
else
o <= i[3*W+:W];
else
if (s[1] == 1'b0)
if (s[2] == 1'b0)
o <= i[4*W+:W];
else
o <= i[5*W+:W];
else
if (s[2] == 1'b0)
o <= i[6*W+:W];
else
o <= i[7*W+:W];
endmodule

15
tests/various/muxpack.ys
View file

@ -133,3 +133,18 @@ design -import gold -as gold
design -import gate -as gate design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top mux_if_bal_8_2
prep
design -save gold
muxpack
opt
stat
select -assert-count 7 t:$mux
select -assert-count 0 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter