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Add one more test with trimming Y_WIDTH of $sub

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This commit is contained in:
Eddie Hung 2019-07-19 13:11:30 -07:00
parent 415a2716df
commit 5bd088a686
1 changed files with 14 additions and 11 deletions
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25
tests/various/wreduce.ys
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@ -9,7 +9,7 @@ hierarchy -auto-top
proc proc
design -save gold design -save gold
prep prep # calls wreduce
select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
@ -21,8 +21,8 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
##########
### X - 0
read_verilog <<EOT read_verilog <<EOT
module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = j - (i << 4); assign o = j - (i << 4);
@ -33,7 +33,7 @@ hierarchy -auto-top
proc proc
design -save gold design -save gold
prep prep # calls wreduce
select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
@ -45,9 +45,10 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
### 0 - X ##########
read_verilog <<EOT read_verilog <<EOT
module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); module wreduce_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = (i << 4) - j; assign o = (i << 4) - j;
endmodule endmodule
EOT EOT
@ -56,7 +57,7 @@ hierarchy -auto-top
proc proc
design -save gold design -save gold
prep prep # calls wreduce
select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
@ -68,10 +69,11 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
### 0 - X ##########
read_verilog <<EOT read_verilog <<EOT
module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); module wreduce_sub_test3(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = (i << 4) - j; assign o = (j >> 4) - i;
endmodule endmodule
EOT EOT
@ -79,9 +81,10 @@ hierarchy -auto-top
proc proc
design -save gold design -save gold
prep prep # calls wreduce
select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i dump
select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
design -stash gate design -stash gate