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Merge pull request #2045 from YosysHQ/eddie/fix2042

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verilog: error if no direction given for task arguments, default to input in SV mode
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Eddie Hung 2020-05-14 09:45:54 -07:00 • committed by GitHub
commit 5bcde7ccc3
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6 changed files with 107 additions and 1 deletions
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14
frontends/verilog/verilog_parser.y
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@ -853,7 +853,19 @@ task_func_port:
}
if (astbuf2 && astbuf2->children.size() != 2)
frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
} wire_name | wire_name;
} wire_name |
{
if (!astbuf1) {
if (!sv_mode)
frontend_verilog_yyerror("task/function argument direction missing");
albuf = new dict<IdString, AstNode*>;
astbuf1 = new AstNode(AST_WIRE);
current_wire_rand = false;
current_wire_const = false;
astbuf1->is_input = true;
astbuf2 = NULL;
}
} wire_name;
task_func_body:
task_func_body behavioral_stmt |