mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

Fixed a verilog parser memory leak

Browse source
This commit is contained in:
Clifford Wolf 2016-07-25 16:37:58 +02:00
parent 7a67add95d
commit 5b944ef11b
1 changed files with 1 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
frontends/verilog/verilog_parser.y
View file

@ -880,6 +880,7 @@ cell_port_list:
if (!node->children.empty()) break;
if (!node->str.empty()) break;
astbuf2->children.pop_back();
delete node;
}
// check port types