mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-27 14:37:55 +00:00
Code Activity

Merge pull request #4959 from YosysHQ/krys/primitive_array_error

Browse source 
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
This commit is contained in:
KrystalDelusion 2025-07-21 10:26:00 +12:00 • committed by GitHub
commit 5b8b5292ee
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
2 changed files with 11 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

9
tests/verilog/bug4785.ys Normal file
View file

@ -0,0 +1,9 @@
logger -expect error "Cell arrays of primitives are currently not supported" 1
read_verilog <<EOT
module test(in1, in2, out1);
input in1, in2;
output out1;
nand #2 t_nand[0:7](out1, in1, in2);
endmodule
EOT