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intel_alm: direct LUTRAM cell instantiation

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By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
This commit is contained in:
Dan Ravensloft 2020-04-16 12:24:04 +01:00 • committed by Marcelina Kościelnicka
parent 0610424940
commit 5b779f7f4e
9 changed files with 163 additions and 52 deletions
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2
techlibs/intel_alm/synth_intel_alm.cc
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@ -164,6 +164,7 @@ struct SynthIntelALMPass : public ScriptPass {
run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str()));
// Misc and common cells
run("read_verilog -lib +/intel/common/altpll_bb.v");
@ -190,7 +191,6 @@ struct SynthIntelALMPass : public ScriptPass {
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V / Cyclone 10GX)");
run("techmap -map +/intel_alm/common/lutram_mlab_map.v", "(for Cyclone V / Cyclone 10GX)");
}
if (check_label("map_ffram")) {