intel_alm: direct LUTRAM cell instantiation

By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.

techlibs/intel_alm/common/lutram_mlab.txt

@@ -1,20 +1,18 @@
-bram __MISTRAL_MLAB
-    init   0   # TODO: Re-enable when I figure out how LUTRAM init works
-    abits  5
-    dbits  16  @D32x16
-    dbits  18  @D32x18
-    dbits  20  @D32x20
-    groups 2
-    ports  1 1
-    wrmode 1 0
-    # read enable
-    enable 1 0
-    transp 1 0
-    clocks 1 2
-    clkpol 1 1
-endbram
-
-match __MISTRAL_MLAB
-    min efficiency 5
-    make_outreg
-endmatch
+bram MISTRAL_MLAB
+    init   0   # TODO: Re-enable when Yosys remembers the original filename.
+    abits  5
+    dbits  1
+    groups 2
+    ports  1 1
+    wrmode 1 0
+    # write enable
+    enable 1 0
+    transp 0 0
+    clocks 1 0
+    clkpol 1 1
+endbram
+
+match MISTRAL_MLAB
+    min efficiency 5
+    make_outreg
+endmatch