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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}

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Eddie Hung 2019-09-27 12:49:57 -07:00 • committed by Marcin Kościelnicki
parent 4535f2c694
commit 5b5756b91e
6 changed files with 46 additions and 122 deletions
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4
techlibs/xilinx/cells_xtra.py
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@ -108,8 +108,8 @@ XC6S_CELLS = [
# Cell('FDRE'),
# Cell('FDSE'),
Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
Cell('LDCE'),
Cell('LDPE'),
# Cell('LDCE'),
# Cell('LDPE'),
Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
# Slice/CLB primitives.