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sigspec: no hash

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This commit is contained in:
Emil J. Tywoniak 2024-07-24 10:40:06 +02:00
parent 49f547782c
commit 5b36c15bc6
2 changed files with 17 additions and 48 deletions
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52
kernel/rtlil.cc
View file

@ -3789,7 +3789,6 @@ RTLIL::SigSpec::SigSpec(std::initializer_list<RTLIL::SigSpec> parts)
cover("kernel.rtlil.sigspec.init.list");
width_ = 0;
hash_ = 0;
log_assert(parts.size() > 0);
auto ie = parts.begin();
@ -3808,7 +3807,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
} else {
width_ = 0;
}
hash_ = 0;
check();
}
@ -3822,7 +3820,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Const &&value)
} else {
width_ = 0;
}
hash_ = 0;
check();
}
@ -3836,7 +3833,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigChunk &chunk)
} else {
width_ = 0;
}
hash_ = 0;
check();
}
@ -3850,7 +3846,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigChunk &&chunk)
} else {
width_ = 0;
}
hash_ = 0;
check();
}
@ -3864,7 +3859,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
} else {
width_ = 0;
}
hash_ = 0;
check();
}
@ -3878,7 +3872,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
} else {
width_ = 0;
}
hash_ = 0;
check();
}
@ -3892,7 +3885,6 @@ RTLIL::SigSpec::SigSpec(const std::string &str)
} else {
width_ = 0;
}
hash_ = 0;
check();
}
@ -3903,7 +3895,6 @@ RTLIL::SigSpec::SigSpec(int val, int width)
if (width != 0)
chunks_.emplace_back(val, width);
width_ = width;
hash_ = 0;
check();
}
@ -3914,7 +3905,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::State bit, int width)
if (width != 0)
chunks_.emplace_back(bit, width);
width_ = width;
hash_ = 0;
check();
}
@ -3930,7 +3920,6 @@ RTLIL::SigSpec::SigSpec(const RTLIL::SigBit &bit, int width)
chunks_.push_back(bit);
}
width_ = width;
hash_ = 0;
check();
}
@ -3939,7 +3928,6 @@ RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigChunk> &chunks)
cover("kernel.rtlil.sigspec.init.stdvec_chunks");
width_ = 0;
hash_ = 0;
for (const auto &c : chunks)
append(c);
check();
@ -3950,7 +3938,6 @@ RTLIL::SigSpec::SigSpec(const std::vector<RTLIL::SigBit> &bits)
cover("kernel.rtlil.sigspec.init.stdvec_bits");
width_ = 0;
hash_ = 0;
for (const auto &bit : bits)
append(bit);
check();
@ -3961,7 +3948,6 @@ RTLIL::SigSpec::SigSpec(const pool<RTLIL::SigBit> &bits)
cover("kernel.rtlil.sigspec.init.pool_bits");
width_ = 0;
hash_ = 0;
for (const auto &bit : bits)
append(bit);
check();
@ -3972,7 +3958,6 @@ RTLIL::SigSpec::SigSpec(const std::set<RTLIL::SigBit> &bits)
cover("kernel.rtlil.sigspec.init.stdset_bits");
width_ = 0;
hash_ = 0;
for (const auto &bit : bits)
append(bit);
check();
@ -3983,7 +3968,6 @@ RTLIL::SigSpec::SigSpec(bool bit)
cover("kernel.rtlil.sigspec.init.bool");
width_ = 0;
hash_ = 0;
append(SigBit(bit));
check();
}
@ -4040,32 +4024,30 @@ void RTLIL::SigSpec::unpack() const
that->bits_.emplace_back(c, i);
that->chunks_.clear();
that->hash_ = 0;
}
void RTLIL::SigSpec::updhash() const
size_t RTLIL::SigSpec::hash() const
{
RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
if (that->hash_ != 0)
return;
cover("kernel.rtlil.sigspec.hash");
that->pack();
that->hash_ = mkhash_init;
long hash_ = mkhash_init;
for (auto &c : that->chunks_)
if (c.wire == NULL) {
for (auto &v : c.data)
that->hash_ = mkhash(that->hash_, v);
hash_ = mkhash(hash_, v);
} else {
that->hash_ = mkhash(that->hash_, c.wire->name.index_);
that->hash_ = mkhash(that->hash_, c.offset);
that->hash_ = mkhash(that->hash_, c.width);
hash_ = mkhash(hash_, c.wire->name.index_);
hash_ = mkhash(hash_, c.offset);
hash_ = mkhash(hash_, c.width);
}
if (that->hash_ == 0)
that->hash_ = 1;
if (hash_ == 0)
hash_ = 1;
return hash_;
}
void RTLIL::SigSpec::sort()
@ -4654,11 +4636,8 @@ bool RTLIL::SigSpec::operator <(const RTLIL::SigSpec &other) const
if (chunks_.size() != other.chunks_.size())
return chunks_.size() < other.chunks_.size();
updhash();
other.updhash();
if (hash_ != other.hash_)
return hash_ < other.hash_;
if (hash() != other.hash())
return hash() < other.hash();
for (size_t i = 0; i < chunks_.size(); i++)
if (chunks_[i] != other.chunks_[i]) {
@ -4692,11 +4671,8 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
if (chunks_.size() != other.chunks_.size())
return false;
updhash();
other.updhash();
if (hash_ != other.hash_)
return false;
if (hash() != other.hash())
return hash() == other.hash();
for (size_t i = 0; i < chunks_.size(); i++)
if (chunks_[i] != other.chunks_[i]) {

13
kernel/rtlil.h
View file

@ -842,13 +842,12 @@ struct RTLIL::SigSpec
{
private:
int width_;
unsigned long hash_;
// unsigned long hash_;
std::vector<RTLIL::SigChunk> chunks_; // LSB at index 0
std::vector<RTLIL::SigBit> bits_; // LSB at index 0
void pack() const;
void unpack() const;
void updhash() const;
inline bool packed() const {
return bits_.empty();
@ -864,7 +863,7 @@ private:
friend struct RTLIL::Module;
public:
SigSpec() : width_(0), hash_(0) {}
SigSpec() : width_(0) {}
SigSpec(std::initializer_list<RTLIL::SigSpec> parts);
SigSpec(const RTLIL::Const &value);
@ -883,11 +882,7 @@ public:
SigSpec(const std::set<RTLIL::SigBit> &bits);
explicit SigSpec(bool bit);
size_t get_hash() const {
if (!hash_) hash();
return hash_;
}
size_t hash() const;
inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }
inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }
@ -994,8 +989,6 @@ public:
operator std::vector<RTLIL::SigBit>() const { return bits(); }
const RTLIL::SigBit &at(int offset, const RTLIL::SigBit &defval) { return offset < width_ ? (*this)[offset] : defval; }
unsigned int hash() const { if (!hash_) updhash(); return hash_; };
#ifndef NDEBUG
void check(Module *mod = nullptr) const;
#else