mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-25 23:33:42 +00:00
Code Activity

ast: fix new memory safety bugs from rebase

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-06-17 15:25:57 +02:00
parent 20225d19ae
commit 5af4e05125
3 changed files with 12 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

4
frontends/ast/genrtlil.cc
View file

@ -1612,7 +1612,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
auto fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
auto fake_ast = std::make_unique<AstNode>(AST_NONE, clone(), children[0]->children.size() >= 2 ?
children[0]->children[1]->clone() : children[0]->children[0]->clone());
fake_ast->children[0]->delete_children();
if (member_node)
@ -1633,7 +1633,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
if (GetSize(shift_val) >= 32)
fake_ast->children[1]->is_signed = true;
RTLIL::SigSpec sig = binop2rtlil(fake_ast, ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
RTLIL::SigSpec sig = binop2rtlil(fake_ast.get(), ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
return sig;
} else {
chunk.width = children[0]->range_left - children[0]->range_right + 1;

2
frontends/ast/simplify.cc
View file

@ -1505,7 +1505,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (children[0]->type == AST_WIRE) {
int width = 1;
std::unique_ptr<AstNode> node;
AstNode* child = children[0].release();
AstNode* child = children[0].get();
if (child->children.size() == 0) {
// Base type (e.g., int)
width = child->range_left - child->range_right +1;