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Revert "verilog: add support for SystemVerilog string literals."

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This reverts commit 5feb1a1752.
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Emil J. Tywoniak 2025-07-10 21:14:38 +02:00
parent 8a76eba891
commit 5ae0120134
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docs/source/using_yosys/verilog.rst
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@ -379,6 +379,3 @@ from SystemVerilog:
will process conditionals using these keywords by annotating their
representation with the appropriate ``full_case`` and/or ``parallel_case``
attributes, which are described above.)
- SystemVerilog string literals are supported (triple-quoted strings and
escape sequences such as line continuations and hex escapes).