mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-19 23:14:44 +00:00
Code Activity

Remove .c_str() from log_cmd_error() and log_file_error() parameters

Browse source
This commit is contained in:
Robert O'Callahan 2025-09-16 22:59:08 +00:00
parent b95549b469
commit 5ac6858f26
59 changed files with 163 additions and 163 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/techmap/abc.cc
View file

@ -988,7 +988,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
}
if (dff_mode && clk_sig.empty())
log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
log_cmd_error("Clock domain %s not found.\n", clk_str);
const AbcConfig &config = run_abc.config;
if (config.cleanup)
@ -2322,7 +2322,7 @@ struct AbcPass : public Pass {
if (g_arg_from_cmd)
cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g));
else
log_cmd_error("Unsupported gate type: %s", g.c_str());
log_cmd_error("Unsupported gate type: %s", g);
ok_gate:
gate_list.push_back(g);
ok_alias:

2
passes/techmap/cellmatch.cc
View file

@ -173,7 +173,7 @@ struct CellmatchPass : Pass {
derive_luts = true;
} else if (args[argidx] == "-lib" && argidx + 1 < args.size()) {
if (!saved_designs.count(args[++argidx]))
log_cmd_error("No design '%s' found!\n", args[argidx].c_str());
log_cmd_error("No design '%s' found!\n", args[argidx]);
lib = saved_designs.at(args[argidx]);
} else {
break;

4
passes/techmap/constmap.cc
View file

@ -82,7 +82,7 @@ struct ConstmapPass : public Pass {
}
}
if (!has_port)
log_cmd_error("Cell type '%s' does not have port '%s'.\n", celltype.c_str(), cell_portname.c_str());
log_cmd_error("Cell type '%s' does not have port '%s'.\n", celltype, cell_portname);
bool has_param = false;
for (auto &p : existing->avail_parameters){
@ -91,7 +91,7 @@ struct ConstmapPass : public Pass {
}
if (!has_param)
log_cmd_error("Cell type '%s' does not have parameter '%s'.\n", celltype.c_str(), cell_paramname.c_str());
log_cmd_error("Cell type '%s' does not have parameter '%s'.\n", celltype, cell_paramname);
}

2
passes/techmap/extract.cc
View file

@ -605,7 +605,7 @@ struct ExtractPass : public Pass {
f.open(filename.c_str());
if (f.fail()) {
delete map;
log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
log_cmd_error("Can't open map file `%s'.\n", filename);
}
Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog"));
f.close();