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Remove .c_str() from log_cmd_error() and log_file_error() parameters

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This commit is contained in:
Robert O'Callahan 2025-09-16 22:59:08 +00:00
parent b95549b469
commit 5ac6858f26
59 changed files with 163 additions and 163 deletions
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16
passes/sat/eval.cc
View file

@ -94,11 +94,11 @@ struct BruteForceEquivChecker
continue;
if (mod2->wire(w->name) == nullptr)
log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name.c_str());
log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name);
RTLIL::Wire *w2 = mod2->wire(w->name);
if (w->width != w2->width || w->port_input != w2->port_input || w->port_output != w2->port_output)
log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name.c_str());
log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name);
if (w->port_input) {
mod1_inputs.append(w);
@ -454,11 +454,11 @@ struct EvalPass : public Pass {
for (auto &it : sets) {
RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse_sel(lhs, design, module, it.first))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first.c_str());
log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first);
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, it.second))
log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str());
log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second);
if (!rhs.is_fully_const())
log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str());
log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second);
if (lhs.size() != rhs.size())
log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
it.first.c_str(), log_signal(lhs), lhs.size(), it.second.c_str(), log_signal(rhs), rhs.size());
@ -476,7 +476,7 @@ struct EvalPass : public Pass {
for (auto &it : shows) {
RTLIL::SigSpec signal, value, undef;
if (!RTLIL::SigSpec::parse_sel(signal, design, module, it))
log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str());
log_cmd_error("Failed to parse show expression `%s'.\n", it);
value = signal;
if (set_undef) {
while (!ce.eval(value, undef)) {
@ -502,14 +502,14 @@ struct EvalPass : public Pass {
for (auto &it : shows) {
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, it))
log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str());
log_cmd_error("Failed to parse show expression `%s'.\n", it);
signal.append(sig);
}
for (auto &it : tables) {
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, it))
log_cmd_error("Failed to parse table expression `%s'.\n", it.c_str());
log_cmd_error("Failed to parse table expression `%s'.\n", it);
tabsigs.append(sig);
}

14
passes/sat/miter.cc
View file

@ -76,11 +76,11 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]);
if (design->module(gold_name) == nullptr)
log_cmd_error("Can't find gold module %s!\n", gold_name.c_str());
log_cmd_error("Can't find gold module %s!\n", gold_name);
if (design->module(gate_name) == nullptr)
log_cmd_error("Can't find gate module %s!\n", gate_name.c_str());
log_cmd_error("Can't find gate module %s!\n", gate_name);
if (design->module(miter_name) != nullptr)
log_cmd_error("There is already a module %s!\n", miter_name.c_str());
log_cmd_error("There is already a module %s!\n", miter_name);
RTLIL::Module *gold_module = design->module(gold_name);
RTLIL::Module *gate_module = design->module(gate_name);
@ -105,7 +105,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
goto match_gold_port_error;
continue;
match_gold_port_error:
log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name.c_str());
log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name);
}
for (auto gate_wire : gate_module->wires()) {
@ -125,7 +125,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
goto match_gate_port_error;
continue;
match_gate_port_error:
log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name.c_str());
log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name);
}
log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name));
@ -322,9 +322,9 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
IdString miter_name = argidx < args.size() ? RTLIL::escape_id(args[argidx++]) : "";
if (design->module(module_name) == nullptr)
log_cmd_error("Can't find module %s!\n", module_name.c_str());
log_cmd_error("Can't find module %s!\n", module_name);
if (!miter_name.empty() && design->module(miter_name) != nullptr)
log_cmd_error("There is already a module %s!\n", miter_name.c_str());
log_cmd_error("There is already a module %s!\n", miter_name);
Module *module = design->module(module_name);

2
passes/sat/mutate.cc
View file

@ -989,7 +989,7 @@ struct MutatePass : public Pass {
return;
}
log_cmd_error("Invalid mode: %s\n", opts.mode.c_str());
log_cmd_error("Invalid mode: %s\n", opts.mode);
}
} MutatePass;

8
passes/sat/qbfsat.cc
View file

@ -87,7 +87,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) {
if (!std::regex_search(buf, bit_m, hole_bit_assn_regex)) {
bit_assn = false;
if (!std::regex_search(buf, m, hole_assn_regex))
log_cmd_error("solution file is not formatted correctly: \"%s\"\n", buf.c_str());
log_cmd_error("solution file is not formatted correctly: \"%s\"\n", buf);
}
std::string hole_loc = bit_assn? bit_m[1].str() : m[1].str();
@ -108,7 +108,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) {
pool<std::string> hole_loc_pool(locs.begin(), locs.end());
auto hole_cell_it = anyconst_loc_to_cell.find(hole_loc_pool);
if (hole_cell_it == anyconst_loc_to_cell.end())
log_cmd_error("cannot find matching wire name or $anyconst cell location for hole spec \"%s\"\n", buf.c_str());
log_cmd_error("cannot find matching wire name or $anyconst cell location for hole spec \"%s\"\n", buf);
RTLIL::Cell *hole_cell = hole_cell_it->second;
hole_sigbit = hole_cell->getPort(ID::Y)[hole_bit];
@ -420,7 +420,7 @@ QbfSolveOptions parse_args(const std::vector<std::string> &args) {
else if (args[opt.argidx+1] == "cvc5")
opt.solver = opt.Solver::CVC5;
else
log_cmd_error("Unknown solver \"%s\".\n", args[opt.argidx+1].c_str());
log_cmd_error("Unknown solver \"%s\".\n", args[opt.argidx+1]);
opt.argidx++;
}
continue;
@ -457,7 +457,7 @@ QbfSolveOptions parse_args(const std::vector<std::string> &args) {
opt.oflag = opt.OptimizationLevel::O2;
break;
default:
log_cmd_error("unknown argument %s\n", args[opt.argidx].c_str());
log_cmd_error("unknown argument %s\n", args[opt.argidx]);
}
continue;
}

44
passes/sat/sat.cc
View file

@ -106,9 +106,9 @@ struct SatHelper
RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first);
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second);
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
@ -127,9 +127,9 @@ struct SatHelper
RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first);
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second);
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
@ -148,7 +148,7 @@ struct SatHelper
RTLIL::SigSpec lhs;
if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.c_str());
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s);
show_signal_pool.add(sigmap(lhs));
log("Import unset-constraint for this timestep: %s\n", log_signal(lhs));
@ -167,28 +167,28 @@ struct SatHelper
for (auto &s : sets_def) {
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
log_cmd_error("Failed to parse set-def expression `%s'.\n", s);
sets_def_undef[0].insert(sig);
}
for (auto &s : sets_any_undef) {
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
log_cmd_error("Failed to parse set-def expression `%s'.\n", s);
sets_def_undef[1].insert(sig);
}
for (auto &s : sets_all_undef) {
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
log_cmd_error("Failed to parse set-def expression `%s'.\n", s);
sets_def_undef[2].insert(sig);
}
for (auto &s : sets_def_at[timestep]) {
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
log_cmd_error("Failed to parse set-def expression `%s'.\n", s);
sets_def_undef[0].insert(sig);
sets_def_undef[1].erase(sig);
sets_def_undef[2].erase(sig);
@ -197,7 +197,7 @@ struct SatHelper
for (auto &s : sets_any_undef_at[timestep]) {
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
log_cmd_error("Failed to parse set-def expression `%s'.\n", s);
sets_def_undef[0].erase(sig);
sets_def_undef[1].insert(sig);
sets_def_undef[2].erase(sig);
@ -206,7 +206,7 @@ struct SatHelper
for (auto &s : sets_all_undef_at[timestep]) {
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
log_cmd_error("Failed to parse set-def expression `%s'.\n", s);
sets_def_undef[0].erase(sig);
sets_def_undef[1].erase(sig);
sets_def_undef[2].insert(sig);
@ -295,9 +295,9 @@ struct SatHelper
RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first);
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second);
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
@ -362,9 +362,9 @@ struct SatHelper
RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
log_cmd_error("Failed to parse lhs proof expression `%s'.\n", s.first.c_str());
log_cmd_error("Failed to parse lhs proof expression `%s'.\n", s.first);
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
log_cmd_error("Failed to parse rhs proof expression `%s'.\n", s.second.c_str());
log_cmd_error("Failed to parse rhs proof expression `%s'.\n", s.second);
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
@ -390,9 +390,9 @@ struct SatHelper
RTLIL::SigSpec lhs, rhs;
if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
log_cmd_error("Failed to parse lhs proof-x expression `%s'.\n", s.first.c_str());
log_cmd_error("Failed to parse lhs proof-x expression `%s'.\n", s.first);
if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
log_cmd_error("Failed to parse rhs proof-x expression `%s'.\n", s.second.c_str());
log_cmd_error("Failed to parse rhs proof-x expression `%s'.\n", s.second);
show_signal_pool.add(sigmap(lhs));
show_signal_pool.add(sigmap(rhs));
@ -540,7 +540,7 @@ struct SatHelper
for (auto &s : shows) {
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
log_cmd_error("Failed to parse show expression `%s'.\n", s.c_str());
log_cmd_error("Failed to parse show expression `%s'.\n", s);
log("Import show expression: %s\n", log_signal(sig));
modelSig.append(sig);
}
@ -670,7 +670,7 @@ struct SatHelper
rewrite_filename(vcd_file_name);
FILE *f = fopen(vcd_file_name.c_str(), "w");
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name.c_str(), strerror(errno));
log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name, strerror(errno));
log("Dumping SAT model to VCD file %s\n", vcd_file_name);
@ -775,7 +775,7 @@ struct SatHelper
rewrite_filename(json_file_name);
FILE *f = fopen(json_file_name.c_str(), "w");
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name.c_str(), strerror(errno));
log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name, strerror(errno));
log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name);
@ -1535,7 +1535,7 @@ struct SatPass : public Pass {
rewrite_filename(cnf_file_name);
FILE *f = fopen(cnf_file_name.c_str(), "w");
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno));
log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name, strerror(errno));
log("Dumping CNF to file `%s'.\n", cnf_file_name);
cnf_file_name.clear();
@ -1639,7 +1639,7 @@ struct SatPass : public Pass {
rewrite_filename(cnf_file_name);
FILE *f = fopen(cnf_file_name.c_str(), "w");
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno));
log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name, strerror(errno));
log("Dumping CNF to file `%s'.\n", cnf_file_name);
cnf_file_name.clear();

2
passes/sat/sim.cc
View file

@ -2887,7 +2887,7 @@ struct SimPass : public Pass {
} else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".yw") == 0) {
worker.run_cosim_yw_witness(top_mod, append);
} else {
log_cmd_error("Unhandled extension for simulation input file `%s`.\n", worker.sim_filename.c_str());
log_cmd_error("Unhandled extension for simulation input file `%s`.\n", worker.sim_filename);
}
}