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Remove .c_str() from log_cmd_error() and log_file_error() parameters

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This commit is contained in:
Robert O'Callahan 2025-09-16 22:59:08 +00:00
parent b95549b469
commit 5ac6858f26
59 changed files with 163 additions and 163 deletions
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4
passes/cmds/abstract.cc
View file

@ -53,7 +53,7 @@ struct Slice {
}
static void syntax_error(const std::string &slice) {
log_cmd_error("Invalid slice '%s', expected '<first>:<last>' or '<single>'", slice.c_str());
log_cmd_error("Invalid slice '%s', expected '<first>:<last>' or '<single>'", slice);
}
std::string to_string() const {
@ -494,7 +494,7 @@ struct AbstractPass : public Pass {
case Enable::ActiveHigh: {
Wire *enable_wire = mod->wire("\\" + enable_name);
if (!enable_wire)
log_cmd_error("Enable wire %s not found in module %s\n", enable_name.c_str(), mod->name.c_str());
log_cmd_error("Enable wire %s not found in module %s\n", enable_name, mod->name);
if (GetSize(enable_wire) != 1)
log_cmd_error("Enable wire %s must have width 1 but has width %d in module %s\n",
enable_name.c_str(), GetSize(enable_wire), mod->name.c_str());

2
passes/cmds/add.cc
View file

@ -77,7 +77,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
wire = nullptr;
if (wire == nullptr)
log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
log_cmd_error("Found incompatible object with same name in module %s!\n", module->name);
log("Module %s already has such an object.\n", module->name);
}

10
passes/cmds/connect.cc
View file

@ -150,9 +150,9 @@ struct ConnectPass : public Pass {
RTLIL::SigSpec sig_lhs, sig_rhs;
if (!RTLIL::SigSpec::parse_sel(sig_lhs, design, module, set_lhs))
log_cmd_error("Failed to parse set lhs expression `%s'.\n", set_lhs.c_str());
log_cmd_error("Failed to parse set lhs expression `%s'.\n", set_lhs);
if (!RTLIL::SigSpec::parse_rhs(sig_lhs, sig_rhs, module, set_rhs))
log_cmd_error("Failed to parse set rhs expression `%s'.\n", set_rhs.c_str());
log_cmd_error("Failed to parse set rhs expression `%s'.\n", set_rhs);
sigmap.apply(sig_lhs);
sigmap.apply(sig_rhs);
@ -173,7 +173,7 @@ struct ConnectPass : public Pass {
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, unset_expr))
log_cmd_error("Failed to parse unset expression `%s'.\n", unset_expr.c_str());
log_cmd_error("Failed to parse unset expression `%s'.\n", unset_expr);
sigmap.apply(sig);
unset_drivers(design, module, sigmap, sig);
@ -185,11 +185,11 @@ struct ConnectPass : public Pass {
log_cmd_error("Can't use -port together with -nounset.\n");
if (module->cell(RTLIL::escape_id(port_cell)) == nullptr)
log_cmd_error("Can't find cell %s.\n", port_cell.c_str());
log_cmd_error("Can't find cell %s.\n", port_cell);
RTLIL::SigSpec sig;
if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
log_cmd_error("Failed to parse port expression `%s'.\n", port_expr);
if (!flag_assert) {
module->cell(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig));

4
passes/cmds/connwrappers.cc
View file

@ -42,7 +42,7 @@ struct ConnwrappersWorker
decl_celltypes.insert(key.first);
if (decls.count(key))
log_cmd_error("Duplicate port decl: %s %s\n", celltype.c_str(), portname.c_str());
log_cmd_error("Duplicate port decl: %s %s\n", celltype, portname);
portdecl_t decl;
decl.widthparam = RTLIL::escape_id(widthparam);
@ -57,7 +57,7 @@ struct ConnwrappersWorker
decl_celltypes.insert(key.first);
if (decls.count(key))
log_cmd_error("Duplicate port decl: %s %s\n", celltype.c_str(), portname.c_str());
log_cmd_error("Duplicate port decl: %s %s\n", celltype, portname);
portdecl_t decl;
decl.widthparam = RTLIL::escape_id(widthparam);

4
passes/cmds/copy.cc
View file

@ -45,10 +45,10 @@ struct CopyPass : public Pass {
std::string trg_name = RTLIL::escape_id(args[2]);
if (design->module(src_name) == nullptr)
log_cmd_error("Can't find source module %s.\n", src_name.c_str());
log_cmd_error("Can't find source module %s.\n", src_name);
if (design->module(trg_name) != nullptr)
log_cmd_error("Target module name %s already exists.\n", trg_name.c_str());
log_cmd_error("Target module name %s already exists.\n", trg_name);
RTLIL::Module *new_mod = design->module(src_name)->clone();
new_mod->name = trg_name;

2
passes/cmds/cover.cc
View file

@ -118,7 +118,7 @@ struct CoverPass : public Pass {
if (f == NULL) {
for (auto f : out_files)
fclose(f);
log_cmd_error("Can't create file %s%s.\n", args[argidx-1] == "-d" ? "in directory " : "", args[argidx].c_str());
log_cmd_error("Can't create file %s%s.\n", args[argidx-1] == "-d" ? "in directory " : "", args[argidx]);
}
out_files.push_back(f);
continue;

8
passes/cmds/design.cc
View file

@ -165,13 +165,13 @@ struct DesignPass : public Pass {
got_mode = true;
load_name = args[++argidx];
if (saved_designs.count(load_name) == 0)
log_cmd_error("No saved design '%s' found!\n", load_name.c_str());
log_cmd_error("No saved design '%s' found!\n", load_name);
continue;
}
if (!got_mode && args[argidx] == "-copy-from" && argidx+1 < args.size()) {
got_mode = true;
if (saved_designs.count(args[++argidx]) == 0)
log_cmd_error("No saved design '%s' found!\n", args[argidx].c_str());
log_cmd_error("No saved design '%s' found!\n", args[argidx]);
copy_from_design = saved_designs.at(args[argidx]);
copy_to_design = design;
continue;
@ -188,7 +188,7 @@ struct DesignPass : public Pass {
got_mode = true;
import_mode = true;
if (saved_designs.count(args[++argidx]) == 0)
log_cmd_error("No saved design '%s' found!\n", args[argidx].c_str());
log_cmd_error("No saved design '%s' found!\n", args[argidx]);
copy_from_design = saved_designs.at(args[argidx]);
copy_to_design = design;
as_name = args[argidx];
@ -202,7 +202,7 @@ struct DesignPass : public Pass {
got_mode = true;
delete_name = args[++argidx];
if (saved_designs.count(delete_name) == 0)
log_cmd_error("No saved design '%s' found!\n", delete_name.c_str());
log_cmd_error("No saved design '%s' found!\n", delete_name);
continue;
}
break;

8
passes/cmds/exec.cc
View file

@ -127,7 +127,7 @@ struct ExecPass : public Pass {
x.re = YS_REGEX_COMPILE(args[argidx]);
expect_stdout.push_back(x);
} catch (const std::regex_error& e) {
log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str());
log_cmd_error("Error in regex expression '%s' !\n", args[argidx]);
}
} else if (args[argidx] == "-not-expect-stdout") {
flag_expect_stdout = true;
@ -142,11 +142,11 @@ struct ExecPass : public Pass {
x.polarity = false;
expect_stdout.push_back(x);
} catch (const std::regex_error& e) {
log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str());
log_cmd_error("Error in regex expression '%s' !\n", args[argidx]);
}
} else
log_cmd_error("Unknown option \"%s\" or \"--\" doesn\'t precede command.\n", args[argidx].c_str());
log_cmd_error("Unknown option \"%s\" or \"--\" doesn\'t precede command.\n", args[argidx]);
}
}
@ -201,7 +201,7 @@ struct ExecPass : public Pass {
if (flag_expect_stdout)
for (auto &x : expect_stdout)
if (x.polarity ^ x.matched)
log_cmd_error("Command stdout did%s have a line matching given regex \"%s\".\n", (x.polarity? " not" : ""), x.str.c_str());
log_cmd_error("Command stdout did%s have a line matching given regex \"%s\".\n", (x.polarity? " not" : ""), x.str);
log_pop();
}

2
passes/cmds/glift.cc
View file

@ -184,7 +184,7 @@ private:
for(auto &cell : module->cells().to_vector()) {
if (!cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_MUX_), ID($_NMUX_), ID($_NOT_), ID($anyconst), ID($allconst), ID($assume), ID($assert)) && module->design->module(cell->type) == nullptr) {
log_cmd_error("Unsupported cell type \"%s\" found. Run `techmap` first.\n", cell->type.c_str());
log_cmd_error("Unsupported cell type \"%s\" found. Run `techmap` first.\n", cell->type);
}
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) {
const unsigned int A = 0, B = 1, Y = 2;

8
passes/cmds/logger.cc
View file

@ -112,7 +112,7 @@ struct LoggerPass : public Pass {
log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str());
log_cmd_error("Error in regex expression '%s' !\n", pattern);
}
continue;
}
@ -124,7 +124,7 @@ struct LoggerPass : public Pass {
log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str());
log_cmd_error("Error in regex expression '%s' !\n", pattern);
}
continue;
}
@ -136,7 +136,7 @@ struct LoggerPass : public Pass {
log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str());
log_cmd_error("Error in regex expression '%s' !\n", pattern);
}
continue;
}
@ -188,7 +188,7 @@ struct LoggerPass : public Pass {
else log_abort();
}
catch (const std::regex_error& e) {
log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str());
log_cmd_error("Error in regex expression '%s' !\n", pattern);
}
continue;
}

4
passes/cmds/plugin.cc
View file

@ -70,7 +70,7 @@ void load_plugin(std::string filename, std::vector<std::string> aliases)
if(module_p == NULL)
{
PyErr_Print();
log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str());
log_cmd_error("Can't load python module `%s'\n", full_path.filename());
return;
}
loaded_python_plugins[orig_filename] = module_p;
@ -100,7 +100,7 @@ void load_plugin(std::string filename, std::vector<std::string> aliases)
}
if (hdl == NULL)
log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror());
log_cmd_error("Can't load module `%s': %s\n", filename, dlerror());
loaded_plugins[orig_filename] = hdl;
Pass::init_register();

6
passes/cmds/rename.cc
View file

@ -31,7 +31,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
to_name = RTLIL::escape_id(to_name);
if (module->count_id(to_name))
log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str());
log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name, module->name);
RTLIL::Wire *wire_to_rename = module->wire(from_name);
RTLIL::Cell *cell_to_rename = module->cell(from_name);
@ -55,7 +55,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
return;
}
log_cmd_error("Object `%s' not found!\n", from_name.c_str());
log_cmd_error("Object `%s' not found!\n", from_name);
}
static std::string derive_name_from_src(const std::string &src, int counter)
@ -632,7 +632,7 @@ struct RenamePass : public Pass {
log("Renaming module %s to %s.\n", module_to_rename->name, to_name);
design->rename(module_to_rename, to_name);
} else
log_cmd_error("Object `%s' not found!\n", from_name.c_str());
log_cmd_error("Object `%s' not found!\n", from_name);
}
}
}

14
passes/cmds/select.cc
View file

@ -592,7 +592,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
while (pos < int(arg.size())) {
if (arg[pos] != ':' || pos+1 == int(arg.size()))
log_cmd_error("Syntax error in expand operator '%s'.\n", arg.c_str());
log_cmd_error("Syntax error in expand operator '%s'.\n", arg);
pos++;
if (arg[pos] == '+' || arg[pos] == '-') {
expand_rule_t rule;
@ -617,7 +617,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
for (auto i2 : i1.second)
limits.insert(i2);
} else
log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str).c_str());
log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str));
} else
limits.insert(RTLIL::escape_id(str));
}
@ -804,7 +804,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
log_cmd_error("Must have at least one element on the stack for operator %%coe.\n");
select_op_expand(design, arg, 'o', true);
} else
log_cmd_error("Unknown selection operator '%s'.\n", arg.c_str());
log_cmd_error("Unknown selection operator '%s'.\n", arg);
if (work_stack.size() >= 1)
select_filter_active_mod(design, work_stack.back());
return;
@ -815,7 +815,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
if (design->selection_vars.count(set_name) > 0)
work_stack.push_back(design->selection_vars[set_name]);
else
log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str());
log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name));
select_filter_active_mod(design, work_stack.back());
return;
}
@ -934,7 +934,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
if (arg_memb.compare(2, 1, "@") == 0) {
std::string set_name = RTLIL::escape_id(arg_memb.substr(3));
if (!design->selection_vars.count(set_name))
log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str());
log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name));
auto &muster = design->selection_vars[set_name];
for (auto cell : mod->cells())
@ -1428,7 +1428,7 @@ struct SelectPass : public Pass {
continue;
}
if (arg.size() > 0 && arg[0] == '-')
log_cmd_error("Unknown option %s.\n", arg.c_str());
log_cmd_error("Unknown option %s.\n", arg);
bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_modcount != -1) ||
(assert_count != -1) || (assert_max != -1) || (assert_min != -1);
select_stmt(design, arg, disable_empty_warning);
@ -1762,7 +1762,7 @@ struct CdPass : public Pass {
return;
}
log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname).c_str());
log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname));
}
} CdPass;

2
passes/cmds/setattr.cc
View file

@ -39,7 +39,7 @@ struct setunset_t
} else {
RTLIL::SigSpec sig_value;
if (!RTLIL::SigSpec::parse(sig_value, nullptr, set_value))
log_cmd_error("Can't decode value '%s'!\n", set_value.c_str());
log_cmd_error("Can't decode value '%s'!\n", set_value);
value = sig_value.as_const();
}
}

2
passes/cmds/setenv.cc
View file

@ -52,7 +52,7 @@ struct SetenvPass : public Pass {
_putenv_s(name.c_str(), value.c_str());
#else
if (setenv(name.c_str(), value.c_str(), 1))
log_cmd_error("Invalid name \"%s\".\n", name.c_str());
log_cmd_error("Invalid name \"%s\".\n", name);
#endif
}

2
passes/cmds/show.cc
View file

@ -926,7 +926,7 @@ struct ShowPass : public Pass {
if (f == nullptr) {
for (auto lib : libs)
delete lib;
log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file);
}
ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_wireshape, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr);
fclose(f);

4
passes/cmds/stat.cc
View file

@ -949,7 +949,7 @@ struct StatPass : public Pass {
}
if (args[argidx] == "-top" && argidx + 1 < args.size()) {
if (design->module(RTLIL::escape_id(args[argidx + 1])) == nullptr)
log_cmd_error("Can't find module %s.\n", args[argidx + 1].c_str());
log_cmd_error("Can't find module %s.\n", args[argidx + 1]);
top_mod = design->module(RTLIL::escape_id(args[++argidx]));
continue;
}
@ -969,7 +969,7 @@ struct StatPass : public Pass {
log_header(design, "Printing statistics.\n");
if (techname != "" && techname != "xilinx" && techname != "cmos" && !json_mode)
log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
log_cmd_error("Unsupported technology: '%s'\n", techname);
if (json_mode) {
log("{\n");

2
passes/cmds/tee.cc
View file

@ -83,7 +83,7 @@ struct TeePass : public Pass {
if (f == NULL) {
for (auto cf : files_to_close)
fclose(cf);
log_cmd_error("Can't create file %s.\n", args[argidx].c_str());
log_cmd_error("Can't create file %s.\n", args[argidx]);
}
log_files.push_back(f);
files_to_close.push_back(f);

2
passes/cmds/viz.cc
View file

@ -994,7 +994,7 @@ struct VizPass : public Pass {
if (f != nullptr) return;
f = fopen(dot_file.c_str(), "w");
if (f == nullptr)
log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file);
};
for (auto module : modlist) {
VizWorker worker(module, config);