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https://github.com/YosysHQ/yosys
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Remove .c_str() from log_cmd_error() and log_file_error() parameters
This commit is contained in:
parent
b95549b469
commit
5ac6858f26
59 changed files with 163 additions and 163 deletions
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@ -1469,7 +1469,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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if (design->has(module_name)) {
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if (!nl->IsOperator() && !is_blackbox(nl))
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log_cmd_error("Re-definition of module `%s'.\n", netlist_name.c_str());
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log_cmd_error("Re-definition of module `%s'.\n", netlist_name);
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return;
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}
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@ -3824,7 +3824,7 @@ struct VerificPass : public Pass {
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add_units_to_map(map, work, flag_lib);
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std::string filename = frontent_rewrite(args, argidx, tmp_files);
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if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_87))
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log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename.c_str());
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log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename);
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set_units_to_blackbox(map, work, flag_lib);
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}
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verific_import_pending = true;
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@ -3849,7 +3849,7 @@ struct VerificPass : public Pass {
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add_units_to_map(map, work, flag_lib);
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std::string filename = frontent_rewrite(args, argidx, tmp_files);
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if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_93))
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log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename.c_str());
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log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename);
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set_units_to_blackbox(map, work, flag_lib);
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}
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verific_import_pending = true;
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@ -3874,7 +3874,7 @@ struct VerificPass : public Pass {
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add_units_to_map(map, work, flag_lib);
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std::string filename = frontent_rewrite(args, argidx, tmp_files);
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if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2K))
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log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename.c_str());
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log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename);
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set_units_to_blackbox(map, work, flag_lib);
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}
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verific_import_pending = true;
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@ -3899,7 +3899,7 @@ struct VerificPass : public Pass {
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add_units_to_map(map, work, flag_lib);
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std::string filename = frontent_rewrite(args, argidx, tmp_files);
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if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2019))
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log_cmd_error("Reading `%s' in VHDL_2019 mode failed.\n", filename.c_str());
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log_cmd_error("Reading `%s' in VHDL_2019 mode failed.\n", filename);
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set_units_to_blackbox(map, work, flag_lib);
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}
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verific_import_pending = true;
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@ -3924,7 +3924,7 @@ struct VerificPass : public Pass {
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add_units_to_map(map, work, flag_lib);
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std::string filename = frontent_rewrite(args, argidx, tmp_files);
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if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2008))
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log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename.c_str());
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log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename);
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set_units_to_blackbox(map, work, flag_lib);
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}
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verific_import_pending = true;
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@ -3938,7 +3938,7 @@ struct VerificPass : public Pass {
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while (argidx < GetSize(args)) {
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std::string filename = frontent_rewrite(args, argidx, tmp_files);
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if (!edif.Read(filename.c_str()))
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log_cmd_error("Reading `%s' in EDIF mode failed.\n", filename.c_str());
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log_cmd_error("Reading `%s' in EDIF mode failed.\n", filename);
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}
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goto check_error;
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}
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@ -3961,7 +3961,7 @@ struct VerificPass : public Pass {
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while (argidx < GetSize(args)) {
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std::string filename = frontent_rewrite(args, argidx, tmp_files);
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if (!synlib_file::Read(filename.c_str(), is_work_set ? work.c_str() : nullptr))
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log_cmd_error("Reading `%s' in LIBERTY mode failed.\n", filename.c_str());
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log_cmd_error("Reading `%s' in LIBERTY mode failed.\n", filename);
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SynlibLibrary *lib = synlib_file::GetLastLibraryAnalyzed();
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if (lib && flag_lib) {
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MapIter mi ;
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