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Add support for PRIM_SVA_UNTIL to new SVA importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -922,6 +922,33 @@ struct VerificSvaImporter
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consequent_net = consequent_inst->GetInput();
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consequent_net = consequent_inst->GetInput();
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}
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}
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if (consequent_inst && (consequent_inst->Type() == PRIM_SVA_UNTIL || consequent_inst->Type() == PRIM_SVA_S_UNTIL ||
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consequent_inst->Type() == PRIM_SVA_UNTIL_WITH || consequent_inst->Type() == PRIM_SVA_S_UNTIL_WITH))
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{
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bool until_with = consequent_inst->Type() == PRIM_SVA_UNTIL_WITH || consequent_inst->Type() == PRIM_SVA_S_UNTIL_WITH;
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consequent_net = consequent_inst->GetInput1();
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Net *until_net = consequent_inst->GetInput2();
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SvaFsm until_fsm(module, clock, clockpol, disable_iff);
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node = parse_sequence(&until_fsm, until_fsm.startNode, until_net);
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if (until_with) {
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int next_node = until_fsm.createNode();
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until_fsm.createEdge(node, next_node);
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node = next_node;
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}
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until_fsm.createLink(node, until_fsm.acceptNode);
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SigBit until_match = until_fsm.getAccept();
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SigBit not_until_match = module->Not(NEW_ID, until_match);
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Wire *extend_antecedent_match_q = module->addWire(NEW_ID);
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extend_antecedent_match_q->attributes["\\init"] = Const(0, 1);
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antecedent_match = module->Or(NEW_ID, antecedent_match, extend_antecedent_match_q);
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SigBit extend_antecedent_match = module->And(NEW_ID, not_until_match, antecedent_match);
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module->addDff(NEW_ID, clock, extend_antecedent_match, extend_antecedent_match_q, clockpol);
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}
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SvaFsm consequent_fsm(module, clock, clockpol, disable_iff, antecedent_match);
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SvaFsm consequent_fsm(module, clock, clockpol, disable_iff, antecedent_match);
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node = parse_sequence(&consequent_fsm, consequent_fsm.startNode, consequent_net);
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node = parse_sequence(&consequent_fsm, consequent_fsm.startNode, consequent_net);
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consequent_fsm.createLink(node, consequent_fsm.acceptNode);
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consequent_fsm.createLink(node, consequent_fsm.acceptNode);
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