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Add actual DSP inference to ice40_dsp pass

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-02-17 15:35:48 +01:00
parent c06c062469
commit 5a853ed46c
3 changed files with 214 additions and 24 deletions
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18
passes/pmgen/ice40_dsp.pmg
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@ -63,7 +63,7 @@ code sigY clock clock_pol clock_vld
sigY = port(mul, \Y);
if (ffY) {
sigY = port(ffY, \D);
sigY = port(ffY, \Q);
SigBit c = port(ffY, \CLK).as_bit();
bool cp = param(ffY, \CLK_POLARITY).as_bool();
@ -77,7 +77,7 @@ code sigY clock clock_pol clock_vld
endcode
match addA
select addA->type.in($add, $sub)
select addA->type.in($add)
select nusers(port(addA, \A)) == 2
index <SigSpec> port(addA, \A) === sigY
optional
@ -134,3 +134,17 @@ match ffS
index <SigSpec> port(ffS, \D) === port(muxAB, \Y)
index <SigSpec> port(ffS, \Q) === sigS
endmatch
code clock clock_pol clock_vld
if (ffS) {
SigBit c = port(ffS, \CLK).as_bit();
bool cp = param(ffS, \CLK_POLARITY).as_bool();
if (clock_vld && (c != clock || cp != clock_pol))
reject;
clock = c;
clock_pol = cp;
clock_vld = true;
}
endcode