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Fine tune aigerparse

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This commit is contained in:
Eddie Hung 2019-06-07 16:57:32 -07:00
parent 1e201a9b01
commit 5a46a0b385
2 changed files with 32 additions and 63 deletions
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6
passes/techmap/abc9.cc
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@ -586,7 +586,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Cell *cell;
RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
if (!lut_costs.empty() || !lut_file.empty()) {
if (!a_bit.wire) {
c->setPort("\\Y", module->addWire(NEW_ID));
module->connect(module->wires_[remap_name(y_bit.wire->name)], RTLIL::S1);
}
else if (!lut_costs.empty() || !lut_file.empty()) {
RTLIL::Cell* driving_lut = nullptr;
// ABC can return NOT gates that drive POs
if (!a_bit.wire->port_input) {