From 5a33f089bf803eb20bbdedfc0434f583360bec89 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 Apr 2020 16:24:55 -0700
Subject: [PATCH] Cleanup

---
 backends/aiger/xaiger.cc   |  2 +-
 kernel/timinginfo.h        |  1 -
 passes/techmap/abc9_ops.cc | 13 ++++---------
 tests/various/sta.ys       |  2 +-
 4 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index a29b9e694..972da7fcc 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -267,7 +267,7 @@ struct XAigerWriter
 
 #ifndef NDEBUG
 					if (ys_debug(1)) {
-						static std::set<std::pair<IdString,TimingInfo::NameBit>> seen;
+						static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
 						if (seen.emplace(derived_type, i.first).second) log("%s.%s[%d] abc9_arrival = %d\n",
 								log_id(cell->type), log_id(i.first.name), offset, d);
 					}
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 580d36b1a..fcb5c90df 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -36,7 +36,6 @@ struct TimingInfo
 		explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
 		bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
 		bool operator!=(const NameBit& nb) const { return !operator==(nb); }
-		bool operator<(const NameBit& nb) const { return nb.name < name && nb.offset < offset; }
 		unsigned int hash() const { return mkhash_add(name.hash(), offset); }
 	};
 	struct BitBit
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 5e847aeda..11e404616 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -431,14 +431,9 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 		inst_module = design->module(derived_type);
 		log_assert(inst_module);
 
-		auto &t = timing.at(derived_type).required;
-		for (auto &conn : cell->connections_) {
-			auto port_wire = inst_module->wire(conn.first);
-			if (!port_wire)
-				log_error("Port %s in cell %s (type %s) of module %s does not actually exist",
-						log_id(conn.first), log_id(cell->name), log_id(cell->type), log_id(module->name));
-			if (!port_wire->port_input)
-				continue;
+		for (auto &i : timing.at(derived_type).required) {
+			auto port_wire = inst_module->wire(i.first.name);
+			log_assert(port_wire->port_input);
 
 			auto d = i.second.first;
 			if (d == 0)
@@ -449,7 +444,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 			auto rhs = cell->getPort(i.first.name);
 #ifndef NDEBUG
 			if (ys_debug(1)) {
-				static std::set<std::pair<IdString,TimingInfo::NameBit>> seen;
+				static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
 				if (seen.emplace(derived_type, i.first).second) log("%s.%s[%d] abc9_required = %d\n",
 						log_id(cell->type), log_id(i.first.name), offset, d);
 			}
diff --git a/tests/various/sta.ys b/tests/various/sta.ys
index cfb6ff2be..156c31c47 100644
--- a/tests/various/sta.ys
+++ b/tests/various/sta.ys
@@ -56,7 +56,7 @@ const0 c(.o(p));
 endmodule
 EOT
 
-logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1 
+logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1
 sta