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Pack adders not just accumulators

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This commit is contained in:
Eddie Hung 2019-07-22 13:01:49 -07:00
parent 3a7aeb028d
commit 5a14b6e1f6
2 changed files with 33 additions and 16 deletions
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11
passes/pmgen/ice40_dsp.pmg
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@ -1,7 +1,7 @@
pattern ice40_dsp
state <SigBit> clock
state <bool> clock_pol
state <bool> clock_pol sigS_signed
state <SigSpec> sigA sigB sigY sigS
state <Cell*> addAB muxAB
@ -92,14 +92,16 @@ match addB
optional
endmatch
code addAB sigS
code addAB sigS sigS_signed
if (addA) {
addAB = addA;
sigS = port(addA, \B);
sigS = port(addAB, \B);
sigS_signed = param(addAB, \B_SIGNED).as_bool();
}
if (addB) {
addAB = addB;
sigS = port(addB, \A);
sigS = port(addAB, \A);
sigS_signed = param(addAB, \A_SIGNED).as_bool();
}
if (addAB) {
int natural_mul_width = GetSize(sigA) + GetSize(sigB);
@ -144,6 +146,7 @@ match ffS
select nusers(port(ffS, \D)) == 2
index <SigSpec> port(ffS, \D) === port(muxAB, \Y)
index <SigSpec> port(ffS, \Q) === sigS
optional
endmatch
code clock clock_pol