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Fixed handling of parameters and const functions in casex/casez pattern

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This commit is contained in:
Clifford Wolf 2016-04-21 15:31:54 +02:00
parent f38ca3e18f
commit 5a09fa4553
5 changed files with 37 additions and 8 deletions
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8
frontends/verilog/verilog_parser.y
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@ -1094,7 +1094,9 @@ case_body:
case_item:
{
AstNode *node = new AstNode(AST_COND);
AstNode *node = new AstNode(
case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
} case_select {
@ -1114,7 +1116,9 @@ gen_case_body:
gen_case_item:
{
AstNode *node = new AstNode(AST_COND);
AstNode *node = new AstNode(
case_type_stack.size() && case_type_stack.back() == 'x' ? AST_CONDX :
case_type_stack.size() && case_type_stack.back() == 'z' ? AST_CONDZ : AST_COND);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
} case_select {