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Avoid generating wires for function args which are constant

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Zachary Snow 2020-07-24 21:18:24 -06:00
parent dafe04d559
commit 59c4ad8ed3
3 changed files with 73 additions and 0 deletions
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tests/various/const_arg_loop.ys Normal file
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read_verilog const_arg_loop.v