mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-18 10:30:45 +00:00
Add additional help info
This commit is contained in:
parent
6fb80bce15
commit
59b6ac47c9
1 changed files with 2 additions and 0 deletions
|
@ -2439,6 +2439,8 @@ struct VerificPass : public Pass {
|
||||||
log(" verific {-liberty} <liberty-file>..\n");
|
log(" verific {-liberty} <liberty-file>..\n");
|
||||||
log("\n");
|
log("\n");
|
||||||
log("Load the specified Liberty files into Verific.\n");
|
log("Load the specified Liberty files into Verific.\n");
|
||||||
|
log("Default library when -work is not present is one specified in liberty file.\n");
|
||||||
|
log("To use from SystemVerilog or VHDL use -L to specify liberty library.");
|
||||||
log("\n");
|
log("\n");
|
||||||
log(" -lib\n");
|
log(" -lib\n");
|
||||||
log(" only create empty blackbox modules\n");
|
log(" only create empty blackbox modules\n");
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue