mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

Merge dfa8453102 into 0c689091e2

Browse source
This commit is contained in:
George Rennie 2025-03-18 22:48:02 -07:00 • committed by GitHub
commit 59b3b250f6
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
15 changed files with 16 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/svtypes/typedef_initial_and_assign.ys
View file

@ -11,4 +11,4 @@ logger -expect warning "reg '\\var_19' is assigned in a continuous assignment" 1
read_verilog -sv typedef_initial_and_assign.sv
hierarchy; proc; opt; async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

4
tests/svtypes/typedef_struct_port.ys
View file

@ -1,6 +1,6 @@
read_verilog -sv typedef_struct_port.sv
hierarchy; proc; opt; async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all
select -module test_parser
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/various/const_arg_loop.ys
View file

@ -4,4 +4,4 @@ proc
opt -full
select -module top
async2sync
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/various/const_func.ys
View file

@ -5,4 +5,4 @@ flatten
opt -full
select -module top
async2sync
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/various/countbits.ys
View file

@ -5,4 +5,4 @@ flatten
opt -full
select -module top
async2sync
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/various/param_struct.ys
View file

@ -48,4 +48,4 @@ endmodule
EOF
hierarchy; proc; opt
async2sync
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/atom_type_signedness.ys
View file

@ -16,4 +16,4 @@ endmodule
EOT
hierarchy; proc; opt; async2sync
select -module dut
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/int_types.ys
View file

@ -5,4 +5,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/mem_bounds.ys
View file

@ -4,4 +4,4 @@ flatten
opt -full
select -module top
async2sync
sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef
sat -verify -tempinduct -prove-asserts -show-all -enable_undef

2
tests/verilog/param_no_default.ys
View file

@ -5,4 +5,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/parameters_across_files.ys
View file

@ -18,4 +18,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/typedef_across_files.ys
View file

@ -21,4 +21,4 @@ proc
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/typedef_legacy_conflict.ys
View file

@ -35,4 +35,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/unbased_unsized.ys
View file

@ -5,4 +5,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all

2
tests/verilog/unbased_unsized_shift.ys
View file

@ -5,4 +5,4 @@ flatten
opt -full
async2sync
select -module top
sat -verify -seq 1 -tempinduct -prove-asserts -show-all
sat -verify -tempinduct -prove-asserts -show-all