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Added $sr, $dffsr and $dlatch cell types

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This commit is contained in:
Clifford Wolf 2013-10-18 11:56:16 +02:00
parent 9bc703b964
commit 5998c101a4
3 changed files with 80 additions and 49 deletions
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29
backends/verilog/verilog_backend.cc
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@ -573,34 +573,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == "$sr")
{
RTLIL::SigSpec sig_set, sig_reset;
std::string reg_name = cellname(cell);
bool out_is_reg_wire = is_reg_wire(cell->connections["\\Q"], reg_name);
if (!out_is_reg_wire)
fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str());
fprintf(f, "%s" "always @*\n", indent.c_str());
fprintf(f, "%s" " %s <= (%s | ", indent.c_str(), reg_name.c_str(), reg_name.c_str());
dump_cell_expr_port(f, cell, "S", false);
fprintf(f, ") & ~");
dump_cell_expr_port(f, cell, "R", false);
fprintf(f, ";\n");
if (!out_is_reg_wire) {
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->connections["\\Q"]);
fprintf(f, " = %s;\n", reg_name.c_str());
}
return true;
}
// FIXME: $memrd, $memwr, $mem, $fsm
// FIXME: $sr, $dffsr, $dlatch, $memrd, $memwr, $mem, $fsm
return false;
}