From 5987454eac75d6cd0477311c58d78e3b5bd2538f Mon Sep 17 00:00:00 2001
From: williamzhu17 <williammzhu@gmail.com>
Date: Fri, 28 Mar 2025 14:50:02 -0700
Subject: [PATCH] added breaksop-tests

---
 tests/silimate/breaksop.ys | 157 +++++++++++++++++++++++++++++++++++++
 1 file changed, 157 insertions(+)
 create mode 100644 tests/silimate/breaksop.ys

diff --git a/tests/silimate/breaksop.ys b/tests/silimate/breaksop.ys
new file mode 100644
index 000000000..dda8aff6c
--- /dev/null
+++ b/tests/silimate/breaksop.ys
@@ -0,0 +1,157 @@
+log -header "Simple positive case"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [2:0] a,
+  output wire x
+);
+  assign x = a[0] | (a[1] & a[2]);
+endmodule
+EOF
+check -assert
+
+# Generate $sop
+techmap
+abc -sop
+select -assert-count 1 t:$sop
+
+# Check equivalence after breaksop
+equiv_opt -assert breaksop
+
+# Check final design has correct number of gates
+design -load postopt
+select -assert-count 2 t:$reduce_and
+select -assert-count 1 t:$reduce_or
+
+design -reset
+log -pop
+
+
+
+log -header "With negation"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [2:0] a,
+  output wire x
+);
+  assign x = ~a[0] | (~a[1] & ~a[2]);
+endmodule
+EOF
+check -assert
+
+# Generate $sop
+techmap
+abc -sop
+select -assert-count 1 t:$sop
+
+# Check equivalence after breaksop
+equiv_opt -assert breaksop
+
+# Check final design has correct number of gates
+design -load postopt
+write_verilog dump_post.v
+select -assert-count 2 t:$reduce_and
+select -assert-count 1 t:$reduce_or
+
+design -reset
+log -pop
+
+
+
+log -header "More depth"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = (a[0] & a[1]) | (~a[2] & a[3]) | (a[0] & ~a[1] & a[2]);
+endmodule
+EOF
+check -assert
+
+# Generate $sop
+techmap
+abc -sop
+select -assert-count 1 t:$sop
+
+# Check equivalence after breaksop
+equiv_opt -assert breaksop
+
+# Check final design has correct number of gates
+design -load postopt
+select -assert-count 3 t:$reduce_and
+select -assert-count 1 t:$reduce_or
+
+design -reset
+log -pop
+
+
+
+log -header "Only ORs"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = a[0] | a[1] | a[2] | a[3];
+endmodule
+EOF
+check -assert
+
+# Generate $sop
+techmap
+abc -sop
+select -assert-count 1 t:$sop
+
+# Check equivalence after breaksop
+equiv_opt -assert breaksop
+
+# Check final design has correct number of gates
+design -load postopt
+opt     # Run opt to remove unneeded OR gate
+select -assert-count 1 t:$reduce_and
+select -assert-count 0 t:$reduce_or
+
+design -reset
+log -pop
+
+
+
+log -header "With constants"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire [3:0] a,
+  output wire x
+);
+  assign x = (~a[0] & 1'b1) | (a[1] & 1'b0) | (a[2] & a[3]);
+endmodule
+EOF
+check -assert
+
+# Generate $sop
+techmap
+abc -sop
+select -assert-count 1 t:$sop
+
+# Check equivalence after breaksop
+write_verilog dump_pre.v
+equiv_opt -assert breaksop
+
+# Check final design has correct number of gates
+design -load postopt
+opt
+write_verilog dump_post.v
+select -assert-count 2 t:$reduce_and
+select -assert-count 1 t:$reduce_or
+
+design -reset
+log -pop
\ No newline at end of file