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Fixed building verific bindings

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This commit is contained in:
Clifford Wolf 2014-08-12 15:21:06 +02:00
parent cad98bcd89
commit 593264e9ed
2 changed files with 3 additions and 3 deletions
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2
frontends/verific/build_amd64.txt
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@ -6,7 +6,7 @@ only have the i386 eval version of Verific:
1.) Use a Makefile.conf like the following one: 1.) Use a Makefile.conf like the following one:
--snip-- --snip--
CONFIG := clang-debug CONFIG := clang
ENABLE_TCL := 0 ENABLE_TCL := 0
ENABLE_QT4 := 0 ENABLE_QT4 := 0
ENABLE_ABC := 0 ENABLE_ABC := 0

4
frontends/verific/verific.cc
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@ -687,7 +687,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
RTLIL::SigSpec data = operatorOutput(inst, net_map, module); RTLIL::SigSpec data = operatorOutput(inst, net_map, module);
RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memrd"); RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memrd");
cell->parameters["\\MEMID"] = memory->name; cell->parameters["\\MEMID"] = memory->name.str();
cell->parameters["\\CLK_ENABLE"] = false; cell->parameters["\\CLK_ENABLE"] = false;
cell->parameters["\\CLK_POLARITY"] = true; cell->parameters["\\CLK_POLARITY"] = true;
cell->parameters["\\TRANSPARENT"] = false; cell->parameters["\\TRANSPARENT"] = false;
@ -709,7 +709,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
RTLIL::SigSpec data = operatorInput2(inst, net_map); RTLIL::SigSpec data = operatorInput2(inst, net_map);
RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memwr"); RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memwr");
cell->parameters["\\MEMID"] = memory->name; cell->parameters["\\MEMID"] = memory->name.str();
cell->parameters["\\CLK_ENABLE"] = false; cell->parameters["\\CLK_ENABLE"] = false;
cell->parameters["\\CLK_POLARITY"] = true; cell->parameters["\\CLK_POLARITY"] = true;
cell->parameters["\\PRIORITY"] = 0; cell->parameters["\\PRIORITY"] = 0;