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abc9: aAdd test to check $_NOT_s are absorbed
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@ -38,3 +38,15 @@ abc9 -lut 4
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design -load gold
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design -load gold
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scratchpad -copy abc9.script.flow3 abc9.script
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scratchpad -copy abc9.script.flow3 abc9.script
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abc9 -lut 4
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abc9 -lut 4
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design -reset
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read_verilog -icells <<EOT
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module top(input a, b, output o);
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assign o = ~(a & b);
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endmodule
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EOT
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abc9 -lut 4
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clean
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select -assert-count 1 t:$lut
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select -assert-none t:$lut t:* %D
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