diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 52037dcd2..c96718314 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -169,6 +169,20 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
 	log(".\n");
 }
 
+
+template <typename T>
+static void error_at_src(const RTLIL::Design* design, TwineRef src, T msg) {
+	if (src == Twine::Null) {
+		log_error("%s\n", msg);
+	} else {
+		log_error("%s: %s\n", design->twines.str(src).c_str(), msg);
+	}
+}
+template <typename T>
+static void error_at_proc(const RTLIL::Process* proc, T msg) {
+	error_at_src(proc->module->design, proc->src_id(), msg);
+}
+
 void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 {
 	while (1)
@@ -206,14 +220,15 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 				async_rules.emplace_back(rstval, sync);
 			}
 			else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
-				if (sync_edge != NULL && sync_edge != sync)
-					log_error("Multiple edge sensitive events found for this signal!\n");
+				if (sync_edge != NULL && sync_edge != sync) {
+					error_at_src(mod->design, action.src, stringf("Multiple edge sensitive events found for signal %s", log_signal(sig)));
+				}
 				sig.replace(action.lhs, action.rhs, &insig);
 				sync_edge = sync;
 			}
 			else if (sync->type == RTLIL::SyncType::STa) {
 				if (sync_always != NULL && sync_always != sync)
-					log_error("Multiple always events found for this signal!\n");
+					error_at_proc(proc, stringf("Multiple always events found for signal %s", log_signal(sig)));
 				sig.replace(action.lhs, action.rhs, &insig);
 				sync_always = sync;
 			}
@@ -222,7 +237,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 				global_clock = true;
 			}
 			else {
-				log_error("Event with any-edge sensitivity found for this signal!\n");
+				error_at_proc(proc, stringf("Event with any-edge sensitivity found for signal %s", log_signal(sig)));
 			}
 
 			action.lhs.remove2(sig, &action.rhs);
@@ -273,14 +288,14 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 
 		if (sync_always) {
 			if (sync_edge || !async_rules.empty())
-				log_error("Mixed always event with edge and/or level sensitive events!\n");
+				error_at_proc(proc, stringf("Mixed always event with edge and/or level sensitive events for signal %s", log_signal(sig)));
 			log("  created direct connection (no actual register cell created).\n");
 			mod->connect(RTLIL::SigSig(sig, insig));
 			continue;
 		}
 
 		if (!sync_edge && !global_clock)
-			log_error("Missing edge-sensitive event for this signal!\n");
+			error_at_proc(proc, stringf("Missing edge-sensitive event for signal %s", log_signal(sig)));
 
 		// More than one reset value so we derive a dffsr formulation
 		if (async_rules.size() > 1)