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	cxxrtl: remove inaccurate comment. NFC.
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			@ -1425,8 +1425,6 @@ struct CxxrtlWorker {
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					if (cell->getPort(ID(CLK)).is_wire())
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						register_edge_signal(sigmap, cell->getPort(ID(CLK)),
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							cell->parameters[ID(CLK_POLARITY)].as_bool() ? RTLIL::STp : RTLIL::STn);
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					// The $adff and $dffsr cells are level-sensitive, not edge-sensitive (in spite of the fact that they
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					// are inferred from an edge-sensitive Verilog process) and do not correspond to an edge-type sync rule.
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				}
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				// Similar for memory port cells.
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				if (cell->type.in(ID($memrd), ID($memwr))) {
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