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https://github.com/YosysHQ/yosys
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Refactor uses of log_id in pgm files
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parent
c6f53aec5f
commit
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8 changed files with 12 additions and 12 deletions
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@ -44,7 +44,7 @@ endmatch
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code
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log("replacing clock gate pattern in %s with ff: latch=%s, and=%s\n",
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log_id(module), log_id(latch), log_id(and_gate));
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module, latch, and_gate);
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// Add a flip-flop and rewire the AND gate to use the output of this flop
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// instead of the latch. We don't delete the latch in case its output is
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@ -32,7 +32,7 @@ code
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val_y.extend_u0(GetSize(div_y), param(div, \A_SIGNED).as_bool());
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did_something = true;
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log("muldiv pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
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log("muldiv pattern in %s: mul=%s, div=%s\n", module, mul, div);
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module->connect(div_y, val_y);
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autoremove(div);
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accept;
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@ -119,7 +119,7 @@ code
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autoremove(div);
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// Log, fixup, accept
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log("muldiv_const pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
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log("muldiv_const pattern in %s: mul=%s, div=%s\n", module, mul, div);
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mul->fixup_parameters();
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accept;
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endcode
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@ -112,7 +112,7 @@ code
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did_something = true;
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log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \
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log_id(module), log_id(shift), log_id(add), offset);
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module, shift, add, offset);
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SigSpec new_a;
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if(offset<0) {
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@ -99,7 +99,7 @@ code
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}
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did_something = true;
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log("left shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
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log("left shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul);
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int const_factor = mul_const.as_int();
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int new_const_factor = 1 << factor_bits;
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@ -76,7 +76,7 @@ code
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reject;
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did_something = true;
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log("right shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
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log("right shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul);
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int const_factor = mul_const.as_int();
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int new_const_factor = 1 << factor_bits;
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