From 58df27ce7c17ec8881936fea531a4e727a1c1b78 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 14 May 2026 12:21:32 +0200 Subject: [PATCH] Refactor uses of log_id in pgm files --- passes/opt/peepopt_formal_clockgateff.pmg | 2 +- passes/opt/peepopt_muldiv.pmg | 2 +- passes/opt/peepopt_muldiv_c.pmg | 2 +- passes/opt/peepopt_shiftadd.pmg | 2 +- passes/opt/peepopt_shiftmul_left.pmg | 2 +- passes/opt/peepopt_shiftmul_right.pmg | 2 +- techlibs/microchip/microchip_dsp_cascade.pmg | 4 ++-- techlibs/xilinx/xilinx_dsp_cascade.pmg | 8 ++++---- 8 files changed, 12 insertions(+), 12 deletions(-) diff --git a/passes/opt/peepopt_formal_clockgateff.pmg b/passes/opt/peepopt_formal_clockgateff.pmg index 835f68bd8..1f44a2cf4 100644 --- a/passes/opt/peepopt_formal_clockgateff.pmg +++ b/passes/opt/peepopt_formal_clockgateff.pmg @@ -44,7 +44,7 @@ endmatch code log("replacing clock gate pattern in %s with ff: latch=%s, and=%s\n", - log_id(module), log_id(latch), log_id(and_gate)); + module, latch, and_gate); // Add a flip-flop and rewire the AND gate to use the output of this flop // instead of the latch. We don't delete the latch in case its output is diff --git a/passes/opt/peepopt_muldiv.pmg b/passes/opt/peepopt_muldiv.pmg index a4e232342..c7eb8ec95 100644 --- a/passes/opt/peepopt_muldiv.pmg +++ b/passes/opt/peepopt_muldiv.pmg @@ -32,7 +32,7 @@ code val_y.extend_u0(GetSize(div_y), param(div, \A_SIGNED).as_bool()); did_something = true; - log("muldiv pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div)); + log("muldiv pattern in %s: mul=%s, div=%s\n", module, mul, div); module->connect(div_y, val_y); autoremove(div); accept; diff --git a/passes/opt/peepopt_muldiv_c.pmg b/passes/opt/peepopt_muldiv_c.pmg index 2cf9b028b..eb8b31e13 100644 --- a/passes/opt/peepopt_muldiv_c.pmg +++ b/passes/opt/peepopt_muldiv_c.pmg @@ -119,7 +119,7 @@ code autoremove(div); // Log, fixup, accept - log("muldiv_const pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div)); + log("muldiv_const pattern in %s: mul=%s, div=%s\n", module, mul, div); mul->fixup_parameters(); accept; endcode diff --git a/passes/opt/peepopt_shiftadd.pmg b/passes/opt/peepopt_shiftadd.pmg index 58dbefc12..6144e44ef 100644 --- a/passes/opt/peepopt_shiftadd.pmg +++ b/passes/opt/peepopt_shiftadd.pmg @@ -112,7 +112,7 @@ code did_something = true; log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \ - log_id(module), log_id(shift), log_id(add), offset); + module, shift, add, offset); SigSpec new_a; if(offset<0) { diff --git a/passes/opt/peepopt_shiftmul_left.pmg b/passes/opt/peepopt_shiftmul_left.pmg index 607f8368c..383222195 100644 --- a/passes/opt/peepopt_shiftmul_left.pmg +++ b/passes/opt/peepopt_shiftmul_left.pmg @@ -99,7 +99,7 @@ code } did_something = true; - log("left shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); + log("left shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul); int const_factor = mul_const.as_int(); int new_const_factor = 1 << factor_bits; diff --git a/passes/opt/peepopt_shiftmul_right.pmg b/passes/opt/peepopt_shiftmul_right.pmg index 108829d4f..ac0958bb8 100644 --- a/passes/opt/peepopt_shiftmul_right.pmg +++ b/passes/opt/peepopt_shiftmul_right.pmg @@ -76,7 +76,7 @@ code reject; did_something = true; - log("right shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); + log("right shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul); int const_factor = mul_const.as_int(); int new_const_factor = 1 << factor_bits; diff --git a/techlibs/microchip/microchip_dsp_cascade.pmg b/techlibs/microchip/microchip_dsp_cascade.pmg index fa276d5b5..ad359138d 100644 --- a/techlibs/microchip/microchip_dsp_cascade.pmg +++ b/techlibs/microchip/microchip_dsp_cascade.pmg @@ -135,10 +135,10 @@ finally } - log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin)); + log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin); } else { - log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE); + log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", dsp, dsp_pcin, MAX_DSP_CASCADE); } dsp = dsp_pcin; diff --git a/techlibs/xilinx/xilinx_dsp_cascade.pmg b/techlibs/xilinx/xilinx_dsp_cascade.pmg index 9eebd33c3..587de4713 100644 --- a/techlibs/xilinx/xilinx_dsp_cascade.pmg +++ b/techlibs/xilinx/xilinx_dsp_cascade.pmg @@ -114,7 +114,7 @@ finally } dsp_pcin->setPort(\OPMODE, opmode); - log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin)); + log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin); } if (AREG >= 0) { Wire *cascade = module->addWire(NEW_ID, 30); @@ -128,7 +128,7 @@ finally dsp->setParam(\ACASCREG, AREG); dsp_pcin->setParam(\A_INPUT, Const("CASCADE")); - log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin)); + log_debug("ACOUT -> ACIN cascade for %s -> %s\n", dsp, dsp_pcin); } if (BREG >= 0) { Wire *cascade = module->addWire(NEW_ID, 18); @@ -161,11 +161,11 @@ finally dsp_pcin->setParam(\B_INPUT, Const("CASCADE")); } - log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin)); + log_debug("BCOUT -> BCIN cascade for %s -> %s\n", dsp, dsp_pcin); } } else { - log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE); + log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", dsp, dsp_pcin, MAX_DSP_CASCADE); } dsp = dsp_pcin;