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https://github.com/YosysHQ/yosys
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Cleanup
This commit is contained in:
Eddie Hung
parent
463f710066
commit
58dbb28fd3
1 changed files with 109 additions and 13 deletions
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@ -24,12 +24,14 @@
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#if 0
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// Based on &flow3 - better QoR but more experimental
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#define ABC_COMMAND_LUT "&st; &ps -l; "/*"&sweep -v;"*/" &scorr; " \
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"&st; &if {W}; &save; &st; &syn2; &if {W}; &save; &load; "\
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"&st; &if -g -K 6; &dch -f; &if {W}; &save; &load; "\
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"&st; &if -g -K 6; &synch2; &if {W}; &save; &load"
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#define ABC_COMMAND_LUT "&st; &ps -l; &sweep -v; &scorr; " \
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"&st; &if {W}; &save; &st; &syn2; &if {W} -v; &save; &load; "\
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"&st; &if -g -K 6; &dch -f; &if {W} -v; &save; &load; "\
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"&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
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"&mfs; &ps -l"
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#else
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#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps -l; &if {W} {D} -v; &mfs; &ps -l"
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#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs -b; &ps -l"
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//#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &put -v; dch -f; if {W} {D} -vo; mfs2; &get -vm; &ps -l"
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#endif
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@ -570,13 +572,15 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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boxes.emplace_back(cell);
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}
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std::vector<std::pair<RTLIL::Cell*,RTLIL::Cell*>> not_gates;
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dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
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std::map<std::string, int> cell_stats;
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for (auto c : mapped_mod->cells())
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{
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RTLIL::Cell *cell = nullptr;
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if (c->type == "$_NOT_") {
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RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
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RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
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RTLIL::SigBit a_bit = c->getPort("\\A");
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RTLIL::SigBit y_bit = c->getPort("\\Y");
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if (!a_bit.wire) {
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c->setPort("\\Y", module->addWire(NEW_ID));
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RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
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@ -600,14 +604,16 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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}
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if (!driving_lut) {
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// If a driver couldn't be found (could be from PI,
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// or from a box) then implement using a LUT
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// If a driver couldn't be found (could be from PI or box CI)
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// then implement using a LUT
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cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
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RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset),
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RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
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1);
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RTLIL::Const::from_string("01"));
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bit2sinks[cell->getPort("\\A")].push_back(cell);
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}
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else {
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#if 0
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auto driver_a = driving_lut->getPort("\\A").chunks();
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for (auto &chunk : driver_a)
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chunk.wire = module->wires_[remap_name(chunk.wire->name)];
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@ -620,6 +626,19 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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driver_a,
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RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
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driver_lut);
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#elif 0
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cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
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RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset),
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RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
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RTLIL::Const::from_string("01"));
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#else
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cell = module->addCell(remap_name(c->name), "$_NOT_");
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cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset));
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cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
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not_gates.emplace_back(cell, driving_lut);
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#endif
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cell_stats[RTLIL::unescape_id(c->type)]++;
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}
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}
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else {
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@ -627,19 +646,21 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset));
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cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
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cell_stats[RTLIL::unescape_id(c->type)]++;
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log_abort();
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}
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if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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continue;
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}
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cell_stats[RTLIL::unescape_id(c->type)]++;
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RTLIL::Cell *existing_cell = nullptr;
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RTLIL::Cell *existing_cell = nullptr;
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if (c->type == "$lut") {
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if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
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if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT") == RTLIL::Const::from_string("01")) {
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SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
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SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
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module->connect(my_y, my_a);
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if (markgroups) c->attributes["\\abcgroup"] = map_autoidx;
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if (markgroups) c->attributes["\\abcgroup"] = map_autoidx;
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log_abort();
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continue;
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}
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cell = module->addCell(remap_name(c->name), c->type);
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@ -670,6 +691,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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newsig.append(c);
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}
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cell->setPort(conn.first, newsig);
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if (cell->input(conn.first))
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for (auto i : newsig)
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bit2sinks[i].push_back(cell);
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}
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}
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@ -725,6 +750,77 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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}
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}
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for (auto i : not_gates) {
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RTLIL::Cell *not_cell = i.first;
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auto driving_lut = i.second;
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log_assert(driving_lut);
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RTLIL::SigBit a_bit = not_cell->getPort("\\A");
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RTLIL::SigBit y_bit = not_cell->getPort("\\Y");
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driving_lut = module->cell(remap_name(driving_lut->name));
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log_assert(driving_lut);
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RTLIL::Const driver_lut = driving_lut->getParam("\\LUT");
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for (auto &b : driver_lut.bits) {
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if (b == RTLIL::State::S0) b = RTLIL::State::S1;
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else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
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}
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auto it = bit2sinks.find(a_bit);
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if (it == bit2sinks.end())
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goto duplicate_lut;
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for (auto sink_cell : it->second)
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if (sink_cell->type != "$lut")
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goto duplicate_lut;
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//static int count = 0;
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//log_warning("%d\n", count);
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//if (count++ >= 41)
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// goto duplicate_lut;
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for (auto sink_cell : it->second) {
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SigSpec A = sink_cell->getPort("\\A");
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RTLIL::Const mask = sink_cell->getParam("\\LUT");
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int index = 0;
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for (; index < GetSize(A); index++)
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if (A[index] == a_bit)
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break;
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log_assert(index < GetSize(A));
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int i = 0;
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while (i < GetSize(mask)) {
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for (int j = 0; j < (1 << index); j++)
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std::swap(mask[i+j], mask[i+j+(1 << index)]);
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i += 1 << (index+1);
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}
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A[index] = y_bit;
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sink_cell->setPort("\\A", A);
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sink_cell->setParam("\\LUT", mask);
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}
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// FIXME: Since we have rewritten all sink_LUTs,
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// we should be able to continue here
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// and expect the $_NOT_ gate to be optimised
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// away as it will have no sinks...
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//continue;
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duplicate_lut:
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auto not_cell_name = not_cell->name;
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module->remove(not_cell);
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#if 0
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auto driver_a = driving_lut->getPort("\\A").chunks();
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for (auto &chunk : driver_a)
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chunk.wire = module->wires_[remap_name(chunk.wire->name)];
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module->addLut(not_cell_name,
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driver_a,
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y_bit,
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driver_lut);
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#else
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module->addLut(not_cell_name,
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a_bit,
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y_bit,
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RTLIL::Const::from_string("01"));
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#endif
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}
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//log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
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log("ABC RESULTS: input signals: %8d\n", in_wires);
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log("ABC RESULTS: output signals: %8d\n", out_wires);
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