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Added DSP macros
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@ -2,6 +2,7 @@
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* yosys -- Yosys Open SYnthesis Suite
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* yosys -- Yosys Open SYnthesis Suite
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*
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2024 Richard Herveille <richard.herveille@roalogic.com>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* purpose with or without fee is hereby granted, provided that the above
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@ -289,4 +290,57 @@ module fiftyfivenm_pll
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output vcooverrange;
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output vcooverrange;
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output vcounderrange;
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output vcounderrange;
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endmodule // cycloneive_pll
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endmodule // max10_pll
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//rih
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/* MAX10 MULT clearbox model */
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(* blackbox *)
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module fiftyfivenm_mac_mult (
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dataa,
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datab,
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dataout,
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signa,
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signb,
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aclr,
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clk,
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ena
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);
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parameter dataa_clock = "none";
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parameter dataa_width = 18;
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parameter datab_clock = "none";
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parameter datab_width = 18;
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parameter signa_clock = "none";
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parameter signb_clock = "none";
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parameter lpm_type = "fiftyfivenm_mac_mult";
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input [dataa_width -1:0] dataa;
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input [datab_width -1:0] datab;
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output [(dataa_width+datab_width)-1:0] dataout;
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input signa;
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input signb;
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input aclr;
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input clk;
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input ena;
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endmodule : fiftyfivenm_mac_mult
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module fiftyfivenm_mac_out (
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dataa,
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dataout,
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aclr,
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clk,
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ena
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);
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parameter dataa_width = 38;
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parameter output_clock = "none";
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parameter lpm_type = "fiftyfivenm_mac_out";
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input [dataa_width-1:0] dataa;
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output [dataa_width-1:0] dataout;
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input aclr;
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input clk;
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input ena;
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endmodule : fiftyfivenm_mac_out
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