mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 03:32:29 +00:00 
			
		
		
		
	Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
		
							parent
							
								
									32bd0f22ec
								
							
						
					
					
						commit
						584d2030bf
					
				
					 1 changed files with 2 additions and 0 deletions
				
			
		|  | @ -14,6 +14,8 @@ frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l | |||
| 	$(Q) mkdir -p $(dir $@) | ||||
| 	$(P) flex -o frontends/verilog/verilog_lexer.cc $< | ||||
| 
 | ||||
| frontends/verilog/verilog_parser.tab.o: CXXFLAGS += -DYYMAXDEPTH=100000 | ||||
| 
 | ||||
| OBJS += frontends/verilog/verilog_parser.tab.o | ||||
| OBJS += frontends/verilog/verilog_lexer.o | ||||
| OBJS += frontends/verilog/preproc.o | ||||
|  |  | |||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue