mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 17:15:33 +00:00
Code Activity

Various RTLIL::SigSpec related code cleanups

Browse source
This commit is contained in:
Clifford Wolf 2014-07-25 14:23:31 +02:00
parent c762050e7f
commit 5826670009
4 changed files with 55 additions and 47 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/cmds/show.cc
View file

@ -171,13 +171,13 @@ struct ShowWorker
std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true)
{
if (sig.chunks().size() == 0) {
if (SIZE(sig) == 0) {
fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count);
return stringf("v%d", single_idx_count++);
}
if (sig.chunks().size() == 1) {
const RTLIL::SigChunk &c = sig.chunks().front();
if (sig.is_chunk()) {
const RTLIL::SigChunk &c = sig.as_chunk();
if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
if (!range_check || c.wire->width == c.width)
return stringf("n%d", id2num(c.wire->name));