From 5821ca265aec0d3194aa6188844176b5e4edc29e Mon Sep 17 00:00:00 2001
From: YRabbit <rabbit@yrabbit.cyou>
Date: Sat, 29 Mar 2025 14:52:53 +1000
Subject: [PATCH] Gowin. BUGFIX. Restore MUXes.

I mistakenly listed MUXes as unplanned. This did not lead to
catastrophic consequences - all apicula and uLinux examples compile and
work, but the quality of synthesis was significantly reduced, which
affected the compilation time badly.

Restoring the MUXes will bring the compilation time back to normal.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---
 techlibs/gowin/cells_xtra.py     |  3 +-
 techlibs/gowin/cells_xtra_gw1n.v | 47 ++++++++++++++++++++++++++++++++
 techlibs/gowin/cells_xtra_gw2a.v | 47 ++++++++++++++++++++++++++++++++
 techlibs/gowin/cells_xtra_gw5a.v | 47 ++++++++++++++++++++++++++++++++
 4 files changed, 142 insertions(+), 2 deletions(-)

diff --git a/techlibs/gowin/cells_xtra.py b/techlibs/gowin/cells_xtra.py
index be2e0eff3..874ce392a 100644
--- a/techlibs/gowin/cells_xtra.py
+++ b/techlibs/gowin/cells_xtra.py
@@ -26,8 +26,7 @@ _skip = { # These are already described, no need to extract them from the vendor
           'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP',
           'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC', 'DCS', 'EMCU',
           # These are not planned for implementation
-          'MUX2_MUX8', 'MUX2_MUX16', 'MUX2_MUX32', 'MUX4', 'MUX8', 'MUX16',
-          'MUX32', 'DL', 'DLE', 'DLC', 'DLCE', 'DLP', 'DLPE', 'DLN', 'DLNE',
+          'DL', 'DLE', 'DLC', 'DLCE', 'DLP', 'DLPE', 'DLN', 'DLNE',
           'DLNC', 'DLNCE', 'DLNP', 'DLNPE', 'rSDP', 'rSDPX9', 'rROM', 'rROMX9',
           'TLVDS_OEN_BK', 'DLL', 'DCC', 'I3C', 'IODELAYA', 'IODELAYC', 'IODELAYB',
           'SPMI', 'PLLO', 'DCCG', 'MIPI_DPHY_RX', 'CLKDIVG', 'PWRGRD', 'FLASH96KA',
diff --git a/techlibs/gowin/cells_xtra_gw1n.v b/techlibs/gowin/cells_xtra_gw1n.v
index abf2c0493..f6b19caf3 100644
--- a/techlibs/gowin/cells_xtra_gw1n.v
+++ b/techlibs/gowin/cells_xtra_gw1n.v
@@ -1,6 +1,53 @@
 // Created by cells_xtra.py
 
 
+module MUX2_MUX8 (...);
+input I0,I1;
+input S0;
+output O;
+endmodule
+
+
+module MUX2_MUX16 (...);
+input I0,I1;
+input S0;
+output O;
+endmodule
+
+
+module MUX2_MUX32 (...);
+input I0,I1;
+input S0;
+output O;
+endmodule
+
+
+module MUX4 (...);
+input I0, I1, I2, I3;
+input S0, S1;
+output O;
+endmodule
+
+
+module MUX8 (...);
+input I0, I1, I2, I3, I4, I5, I6, I7;
+input S0, S1, S2;
+output O;
+endmodule
+
+
+module MUX16 (...);
+input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
+input S0, S1, S2, S3;
+output O;
+endmodule
+
+module MUX32 (...);
+input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;
+input S0, S1, S2, S3, S4;
+output O;
+endmodule
+
 module LUT5 (...);
 parameter INIT = 32'h00000000;
 input I0, I1, I2, I3, I4;
diff --git a/techlibs/gowin/cells_xtra_gw2a.v b/techlibs/gowin/cells_xtra_gw2a.v
index 5c365f8da..7c77eb1f1 100644
--- a/techlibs/gowin/cells_xtra_gw2a.v
+++ b/techlibs/gowin/cells_xtra_gw2a.v
@@ -1,6 +1,53 @@
 // Created by cells_xtra.py
 
 
+module MUX2_MUX8 (...);
+input I0,I1;
+input S0;
+output O;
+endmodule
+
+
+module MUX2_MUX16 (...);
+input I0,I1;
+input S0;
+output O;
+endmodule
+
+
+module MUX2_MUX32 (...);
+input I0,I1;
+input S0;
+output O;
+endmodule
+
+
+module MUX4 (...);
+input I0, I1, I2, I3;
+input S0, S1;
+output O;
+endmodule
+
+
+module MUX8 (...);
+input I0, I1, I2, I3, I4, I5, I6, I7;
+input S0, S1, S2;
+output O;
+endmodule
+
+
+module MUX16 (...);
+input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
+input S0, S1, S2, S3;
+output O;
+endmodule
+
+module MUX32 (...);
+input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;
+input S0, S1, S2, S3, S4;
+output O;
+endmodule
+
 module LUT5 (...);
 parameter INIT = 32'h00000000;
 input I0, I1, I2, I3, I4;
diff --git a/techlibs/gowin/cells_xtra_gw5a.v b/techlibs/gowin/cells_xtra_gw5a.v
index d19435f85..10c88cc3f 100644
--- a/techlibs/gowin/cells_xtra_gw5a.v
+++ b/techlibs/gowin/cells_xtra_gw5a.v
@@ -1,6 +1,53 @@
 // Created by cells_xtra.py
 
 
+module MUX2_MUX8 (...);
+input I0,I1;
+input S0;
+output O;
+endmodule
+
+
+module MUX2_MUX16 (...);
+input I0,I1;
+input S0;
+output O;
+endmodule
+
+
+module MUX2_MUX32 (...);
+input I0,I1;
+input S0;
+output O;
+endmodule
+
+
+module MUX4 (...);
+input I0, I1, I2, I3;
+input S0, S1;
+output O;
+endmodule
+
+
+module MUX8 (...);
+input I0, I1, I2, I3, I4, I5, I6, I7;
+input S0, S1, S2;
+output O;
+endmodule
+
+
+module MUX16 (...);
+input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
+input S0, S1, S2, S3;
+output O;
+endmodule
+
+module MUX32 (...);
+input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;
+input S0, S1, S2, S3, S4;
+output O;
+endmodule
+
 module LUT5 (...);
 parameter INIT = 32'h00000000;
 input I0, I1, I2, I3, I4;