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Merge branch 'YosysHQ:main' into main

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Akash Levy 2026-01-12 22:52:03 -08:00 • committed by GitHub
commit 58192ad8a6
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13 changed files with 430 additions and 116 deletions
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3
backends/verilog/verilog_backend.cc
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@ -2161,6 +2161,9 @@ void dump_case_actions(std::ostream &f, std::string indent, RTLIL::CaseRule *cs)
bool dump_proc_switch_ifelse(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw)
{
if (sw->cases.empty())
return true;
for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
if ((*it)->compare.size() == 0) {
break;