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Add more correctness tests.

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nella 2026-05-05 20:09:41 +02:00
parent 80bb367941
commit 57eb30cf51
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tests/techmap/abc_new_keep.ys Normal file
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read_verilog <<EOT
module top(input a, input b, output o);
(* keep *) wire w = a & b;
assign o = ~w;
endmodule
EOT
hierarchy -check -top top
proc; opt -fast; techmap
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
select -assert-none t:$_AND_
select -assert-min 1 t:NAND t:NOT t:NOR t:BUF %u