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Add more correctness tests.

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nella 2026-05-05 20:09:41 +02:00
parent 80bb367941
commit 57eb30cf51
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tests/techmap/abc_new_box.ys Normal file
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read_verilog -icells -specify <<EOT
(* abc9_box, blackbox *)
module box1(input i, output o);
specify
(i => o) = 1;
endspecify
endmodule
module top(input a, input b, output o);
wire z;
$_AND_ gate(.A(a), .B(b), .Y(o));
box1 u_box(.i(a), .o(z));
endmodule
EOT
hierarchy -check -top top
abc_new -script "+&scorr;&sweep;&dc2;&dch,-f;&nf,{D}" -liberty ../../examples/cmos/cmos_cells.lib
select -assert-min 1 t:*