3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-04-27 14:23:37 +00:00

Emit valid SMT for stateful designs, fix some cells

This commit is contained in:
Roland Coeurjoly 2024-07-07 21:01:38 +02:00 committed by Emily Schmidt
parent f0f436cbe7
commit 5780357cd9
4 changed files with 306 additions and 183 deletions

View file

@ -2,4 +2,4 @@ my_module_cxxrtl.cc
my_module_functional_cxx.cc
vcd_harness
*.vcd
*.smt2
*.smt2