mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-04 17:17:43 +00:00
Code Activity

Added tests for attributes

Browse source 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-06-03 09:12:51 +02:00
parent a6cadf6318
commit 5739cf5265
9 changed files with 219 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

25
tests/simple/attrib02_port_decl.v Normal file
View file

@ -0,0 +1,25 @@
module bar(clk, rst, inp, out);
(* this_is_clock = 1 *)
input wire clk;
(* this_is_reset = 1 *)
input wire rst;
input wire inp;
(* an_output_register = 1*)
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
module foo(clk, rst, inp, out);
(* this_is_the_master_clock *)
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance (clk, rst, inp, out);
endmodule