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Added tests for attributes

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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-06-03 09:12:51 +02:00
parent a6cadf6318
commit 5739cf5265
9 changed files with 219 additions and 0 deletions
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tests/simple/attrib01_module.v Normal file
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module bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output reg out;
always @(posedge clk)
if (rst) out <= 1'd0;
else out <= ~inp;
endmodule
module foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output wire out;
bar bar_instance (clk, rst, inp, out);
endmodule