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Renamed "aig" to "aigmap"

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This commit is contained in:
Clifford Wolf 2015-06-10 07:24:26 +02:00
parent 85287295b2
commit 56d4822719
3 changed files with 10 additions and 10 deletions
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2
passes/techmap/Makefile.inc
View file

@ -18,7 +18,7 @@ OBJS += passes/techmap/dff2dffe.o
OBJS += passes/techmap/dffinit.o OBJS += passes/techmap/dffinit.o
OBJS += passes/techmap/pmuxtree.o OBJS += passes/techmap/pmuxtree.o
OBJS += passes/techmap/muxcover.o OBJS += passes/techmap/muxcover.o
OBJS += passes/techmap/aig.o OBJS += passes/techmap/aigmap.o
endif endif
GENFILES += passes/techmap/techmap.inc GENFILES += passes/techmap/techmap.inc

10
passes/techmap/aig.cc → passes/techmap/aigmap.cc
View file

@ -23,12 +23,12 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct AigPass : public Pass { struct AigmapPass : public Pass {
AigPass() : Pass("aig", "convert logic to and-inverter circuit") { } AigmapPass() : Pass("aigmap", "map logic to and-inverter-graph circuit") { }
virtual void help() virtual void help()
{ {
log("\n"); log("\n");
log(" aig [options] [selection]\n"); log(" aigmap [options] [selection]\n");
log("\n"); log("\n");
log("Replace all logic cells with circuits made of only $_AND_ and\n"); log("Replace all logic cells with circuits made of only $_AND_ and\n");
log("$_NOT_ cells.\n"); log("$_NOT_ cells.\n");
@ -41,7 +41,7 @@ struct AigPass : public Pass {
{ {
bool nand_mode = false; bool nand_mode = false;
log_header("Executing AIG pass (converting logic to AIG).\n"); log_header("Executing AIGMAP pass (map logic to AIG).\n");
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
@ -144,6 +144,6 @@ struct AigPass : public Pass {
module->remove(cell); module->remove(cell);
} }
} }
} AigPass; } AigmapPass;
PRIVATE_NAMESPACE_END PRIVATE_NAMESPACE_END

8
passes/tests/test_cell.cc
View file

@ -536,8 +536,8 @@ struct TestCellPass : public Pass {
log(" -simlib\n"); log(" -simlib\n");
log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n"); log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n");
log("\n"); log("\n");
log(" -aig\n"); log(" -aigmap\n");
log(" instead of calling \"techmap\", call \"aig\"\n"); log(" instead of calling \"techmap\", call \"aigmap\"\n");
log("\n"); log("\n");
log(" -muxdiv\n"); log(" -muxdiv\n");
log(" when creating test benches with dividers, create an additional mux\n"); log(" when creating test benches with dividers, create an additional mux\n");
@ -603,8 +603,8 @@ struct TestCellPass : public Pass {
techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc"; techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc";
continue; continue;
} }
if (args[argidx] == "-aig") { if (args[argidx] == "-aigmap") {
techmap_cmd = "aig"; techmap_cmd = "aigmap";
continue; continue;
} }
if (args[argidx] == "-muxdiv") { if (args[argidx] == "-muxdiv") {