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Renamed "aig" to "aigmap"

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This commit is contained in:
Clifford Wolf 2015-06-10 07:24:26 +02:00
parent 85287295b2
commit 56d4822719
3 changed files with 10 additions and 10 deletions
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2
passes/techmap/Makefile.inc
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@ -18,7 +18,7 @@ OBJS += passes/techmap/dff2dffe.o
OBJS += passes/techmap/dffinit.o
OBJS += passes/techmap/pmuxtree.o
OBJS += passes/techmap/muxcover.o
OBJS += passes/techmap/aig.o
OBJS += passes/techmap/aigmap.o
endif
GENFILES += passes/techmap/techmap.inc

10
passes/techmap/aig.cc → passes/techmap/aigmap.cc
View file

@ -23,12 +23,12 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct AigPass : public Pass {
AigPass() : Pass("aig", "convert logic to and-inverter circuit") { }
struct AigmapPass : public Pass {
AigmapPass() : Pass("aigmap", "map logic to and-inverter-graph circuit") { }
virtual void help()
{
log("\n");
log(" aig [options] [selection]\n");
log(" aigmap [options] [selection]\n");
log("\n");
log("Replace all logic cells with circuits made of only $_AND_ and\n");
log("$_NOT_ cells.\n");
@ -41,7 +41,7 @@ struct AigPass : public Pass {
{
bool nand_mode = false;
log_header("Executing AIG pass (converting logic to AIG).\n");
log_header("Executing AIGMAP pass (map logic to AIG).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@ -144,6 +144,6 @@ struct AigPass : public Pass {
module->remove(cell);
}
}
} AigPass;
} AigmapPass;
PRIVATE_NAMESPACE_END